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layout to schematic problem

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If I want to use parasitic capacitors of layout instead of mimcap offered by the process, how should I pass LVS? The problem is that when I extract layout capacitor to schematic capacitor (which is a capacitor not provided by the process), I could't get LVS passed.
 

If you use Assura tool for LVS,there is a switch in LVS form that enables you force LVS to ignore some schematic instances that are missing from layout.Try
to find it in the options provided by the tool and read the respective manuals.
 
Thanks very much. I didn't know this switch before.
My problem is actually I had more parasitic capacitance in layout which was not included in schematic. Someone suggested me to use ideal capacitors in simulation before layout and remove them in schematic when I run LVS after layout. This might a solution.
 

My problem is actually I had more parasitic capacitance in layout which was not included in schematic.
Click to expand...

Yes,this is always in effect.Layout produces parasitics (apparently) that make your design deviate (more or less) from the initial schematic simulations.

Someone suggested me to use ideal capacitors in simulation before layout and remove them in schematic when I run LVS after layout
Click to expand...

I think this has no meaning in schematic (pre-layout) simulation...except the case that you will make a good estimation of the introduced parasitics (R,L,C) by-hand,a fact that means lot of time consumption,precision doubts and in this way you cancel the existence of the extraction tool.Usually,to overcome the parasitics that will come from layout we perform some over-design for the critical specs and finally the performance will be reduced by parasitics to the desired point.
 
if you really want to have the ideal capacitors in schematic - you can add user property "lvsIgnore" with boolean value "true"
This way you can keep them in schematic but during LVS they will be ignored.
Just make sure that when simulating with parasitics your netlist does not include also those ideal cpas (depends on what tool u use and how the pex is written)
 
Thanks very much. What I really want is to use and simulate the parasitic capacitance just the way same as the device capacitor. The device capacitance can't meet my requirement in my design. And I agree there have to be more simulation with parasitic capacitance, especially with mismatch considered. So how can you simulate mismatch of parasitic capacitance in post-layout simulation?
 

If your parasitic capacitance has assigned device model (similar to ie polycap or mimcap) you can define monte carlo distribution. It would have to be new model you make though. Then you just run MC mismatch.
 
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