set_max_delay for CDC path

Hi

My design has got 3 clks. In our design there is no logic in the CDC path i.e. in source domain output of block is flopped and sent to destination domain and it is also flopped (by 2 flop synchronizer). So there is not logic between 2 flops.
I know that its standard practice to declare a set_false_path between CDC paths. But can I replace this constraint by set_max_delay ? is there any advantage in doing this? I heard that few designers are using max_delay constraints instead of false path. I can understand that if we have a logic in CDC path then max_delay constraint is useful. But in case of my design where there is no logic in CDC path, will max_delay constraint is required/recommended/harmful/useful ?

Thanks,

It depends on what signal crosses the domain, but, in general, using max_delay is the correct way to implement the clock domain crossing. I know most of the people just set false paths for domain crossing paths, but it's not a good practice since there still is a timing restriction to the domain crossing path doing a handshake.

Hi lostinxlation,
Thanks for your reply. Can you please explain me in detail regarding your statement " but, in general, using max_delay is the correct way to implement the clock domain crossing".
I can understand that if we have a handshake mechanism (lets say data bus is synchronized using this concept), then there is MUX as a combinatorial path between launch flop(source clk domain) and capture flop(destination clk domain). And we need to constraint it properly such that before valid signal reaches to the source domain(after being passed from 2 -stage synchronizer in destination domain) , data should be stable from MUX. So we constrain this MUX with set_max_delay. But lets say you have a FIFO based design, where FIFO is very small and hence you implemented the FIFO memory with Flops. And lets say the output of that FIFO is directly used by a combinational logic in read clk domain. So what will happen to this path when we set constraint set_false-Path ? Sytnehsis tool will not optimize it for timing and hence it is possible that large delay see from lauch to capture. For this path if we can to use set_max_delay, what time period we should use for it.
Please share your thoughts on this.

Thanks,
Regards,
VJ

viju said:

But lets say you have a FIFO based design, where FIFO is very small and hence you implemented the FIFO memory with Flops. And lets say the output of that FIFO is directly used by a combinational logic in read clk domain. So what will happen to this path when we set constraint set_false-Path ? Sytnehsis tool will not optimize it for timing and hence it is possible that large delay see from lauch to capture. For this path if we can to use set_max_delay, what time period we should use for it.
Please share your thoughts on this.

Click to expand...

FIFO must have an array and the output flop that receives the data from the array(usually the output flop is inside the FIFO, but you may have it outside of FIFO). Array is driven by write clock and the output flop is driven by read clock. Output flop captures the data from array when read enable is asserted, therefore, the metastability problem arises when the data from array doesn't get settled before the read enable asserted. Read enable is based on the empty signal, which has at least 2 read cycle latency for synchronization of the write pointer, so that max_delay from all the flops in array to the output flop must be less than 2 read clcok period.

The idea is the same as the domain crossing with handshake and the same max_delay policy as handshake's should be applied to FIFO.

lostinxlation said:

FIFO must have an array and the output flop that receives the data from the array(usually the output flop is inside the FIFO, but you may have it outside of FIFO). Array is driven by write clock and the output flop is driven by read clock. Output flop captures the data from array when read enable is asserted, therefore, the metastability problem arises when the data from array doesn't get settled before the read enable asserted. Read enable is based on the empty signal, which has at least 2 read cycle latency for synchronization of the write pointer, so that max_delay from all the flops in array to the output flop must be less than 2 read clcok period.

The idea is the same as the domain crossing with handshake and the same max_delay policy as handshake's should be applied to FIFO.

Click to expand...

Hello,

thanks for the insights, i found this post really helpful.

please validate/correct my understanding,
if we have a two stage synchronizer on the read pointer, then the max delay in the datapath between two clock domains should be 1 clock period of the destination clock.

but what if we have a three stage read pointer synchronizer, shouldn't the max delay still be 1 destination clock cycle period.??

please explain..i am very confused..

Thanks for your help,