Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

how to analyse the s parameter in LVDS driver

Status
Not open for further replies.
T

thanapandi

Newbie level 6
Joined
Nov 19, 2010
Messages
11
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,283
Activity points
1,347
HI all,
I am designing in LVDS driver.Here i want to calculate the impedance and reflection using s-parameters analysis. i dont know how to analysis for that one.I have some spec for impedance and reflection of transmiter.anyone help for me
 

The LVDS driver is not a small signal amplifier, so my
advice is to stick to the time domain, model the line
and the far end load reasonably. You would probably
see more garbage from intersymbol effects than an
empty-line small signal analysis will even hint of. If you
are concerned about reflections from a multi-drop
arrangement then model that in detail. And so on.

If you want to apply some other analysis, fine. But I
don't think what you're asking for is the way to go,
in terms of showing you the real line behavior as the
receiver will see it.
 

Hi,
Thanks for your comments.Actually this is not small signal model,But in LVDS driver design the impedance matching is important,Otherwise some power lose in the intrerconnects.In my design interconnect impedance is 50 ohm so i want to match transmitter impedance also 50 ohm.So i want to how to calculate the impedance in LVDS driver in s-parameters analysis
 

i am working on LVDS driver design. do you have any ideas on how to do the small signal analysis for the impedance matching?
 

There are different LVDS driver concepts. In TIA PN-4584, no explicite ooutput impedance specification is given. LVDS drivers accoding to this standard are often designed as current sources (Zout >> ZL). IEEE 1596 in constarst assumes 40 - 140 ohm single ended driver impedance, impedance matching still won't apply. For high speed LVDS (> 1Gbit/s or so) source side matching is suggested by an supplementary standard. What's your basic concept?
 

Hi ,
In LVDS driver you can connect the PORT in Across output signal,and put the port impedance for your specified the differential value.This results give a reflection and returnloss value.
 

thanks for your comments. Basically, my concept is to design a 2.4Gbps LVDS driver. The impedance matching should be 50 ohm and i need to prove that the impedance matching of my design is near to 50 ohm. Do you have any journals related to the proving of impedance matching since i couldn't find suitable journals ofr this.
 

Hi
You mention the 50 ohm is single ended so your design differential impedance is 100 ohm.Put 100 Ohm port across LVDS output and caculate the reflection.Herewith i have attached the document is how to calculate reflection to impedance.Please go through it.
 

HI
thanks a lot but i did not see the attached documents in your comment....T.T
 

Hello.
You can simply integrate 100 Ohm resistor across LVDS driver output for impedance matching. But then you should double driver current. It's drawback of this method.
 

Hi ,
what type of termination using your lvds.In my case i am using 100 Ohm end termination.Thats why we are using s-parameter analysis in above mentioned method.I want to know What type of structure using your design.
 

Attachments

  • Smith chart for S11.doc
    153 KB · Views: 93

I don't agree to your impedance calculation. You calculate the magnitude of the complex impedance Zdn =√(.8948*50)^2+(.5225*50)^2 =51.8 Ohm. (|Zdn| would be a clearer notation) That's arithmetically correct, but for ideal transmission line termination, a single ended real impedance of 50 ohm is needed, in other words, a point at the smith chart center. The capacitive impedance component causes reflections, too.
 

Hi,
I shown is just example one.Actually in my case The smith chart the reflection start in unity 1 circle and rotate clockwise in forward direction.because in my case impedance depance on only resistance and capacitance only.

I have one doubt, here which frequency you are matching the impedance.Lower frequency are operating frequency.
 

I have one doubt, here which frequency you are matching the impedance.
Click to expand...
You need a resistive impedance over a wider frequency range. Capacitive impedance can't be matched for wideband pulse signals.
 

FvM said:
You need a resistive impedance over a wider frequency range. Capacitive impedance can't be matched for wideband pulse signals.
Click to expand...
And common practice for LVDS operating over 1 Gbps is to place additional 100 Ohm termination resitor on the driver side and to double driver current (see "LVDS I/O Interface for Gb/s-per-Pin Operation in 0.35-m CMOS" by Andrea Boni et al.)
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top