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I guess you are referring to phase noise here. I cannot give you a step by step procedure but you will have to focus on matching both w/i each stage and among stages. Having the control voltage modulating the current load does not seem as good as modulating the tail current (since the first method relies on matching of separate PMOSs). Other useful points for matching are to use:
- large area diff pair (low offset)
- current sources in strong inversion
- ratioed PMOSs to define positive feedback switching point
- minimize PMOSs Vt mismatch
- verify impact of thermal and 1/f noise using transient noise with MC mismatch sim
- verify impact of PSRR on both rails
- use layout matching tricks if is to be actually implemented
Knowing what process you are using would help to know what to focus on. I am sure you already know most of this but I hope some of it will help