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Level problem for connecting 2.5 LVCMOS to a ADC with Min(VIH)=2.4v

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Hadi-Alik

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Hi all,

I have a question about connecting my Virtex5 FPGA to my ADC board.
Actually my AVNET FPGA board pins have 2.5 v LVCMOS outputs while I would like to send Clk and Cs signal to my ADC boad (using AD1402) which says that minimum VIH (High Level Input Voltage) is 2.4 volt. Do you think I will encounter some problems in reading data from it ?

Cheers
Hadi
 

Hadi-Alik said:
... Do you think I will encounter some problems in reading data from it ?
Click to expand...

Typically: no. But if you fear that the FPGA board's power supply could buckle down, you could still spend pull-up resistors.
 

What about noise and interference? My FPGA is 50 cm away from the ADC and the clk and cs are send via a flat cable?
 

There are level shifter parts in the 74xxx family. They may
have poor TPLH/TPHL symmetry. Perhaps something like a true
differential line driver, with some voltage gain (say, A=2), is
more what you want. If your clock is under 1GHz a current-
feedback amplifier could likely hang with it, there are some
pretty sporty ones out there.

Now I'm not seeing why the ADC must be clocked by the
FPGA other than simplicity. Maybe you would be better off
clocking the ADC with what it wants, and letting the FPGA
see an image of that clock.

That's a fairly long cable, what data rate do you think you
can throw down it with (evidently) CMOS logic drivers?
 

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