[SOLVED] error by modelsim on a simple mux 2 design

hi,
the following is the mux design

module mux_using_assign(
din_0 , // Mux first input
din_1 , // Mux Second input
sel , // Select input
mux_out , // Mux output

);
//-----------Input Ports---------------
input din_0, din_1, sel ;
//-----------Output Ports---------------
output mux_out;
//------------Internal Variables--------
wire mux_out;
wire din_0, din_1, sel;
//-------------Code Start-----------------
assign mux_out = (sel) ? din_1 : din_0;

endmodule //End Of Module mux



the test bench is the following:

module test_mux ;

wire t_mux_out;
reg t_din_0,t_din_1,t_sel;

mux_using_assign(
.t_din_0(din_0),
.t_din_1(din_1),
.t_sel(sel),
.t_mux_out(mux_out)

);



initial
begin
t_din_0 = 0; t_din_1 = 0; t_sel = 0;

#10
t_sel = 1;


$finish;

end

initial
$monitor($stime,,t_mux_out,,t_din_0,,t_din_1,,t_sel);
endmodule


the design compiles successfuly
so does the test bench
but when it tries to simulate it following error

vsim work.test_mux
# vsim work.test_mux
# ** Note: (vsim-3812) Design is being optimized...
# ** Error: t_mux.v(12): Missing instance name in instantiation of 'mux_using_assign'.
# Optimization failed
# Error loading design


what could be wrong

well then i tried the following

include mux_using_assign.v ;
module test_mux ;

wire t_mux_out;
reg t_din_0,t_din_1,t_sel;
mux_using_assign dut(t_din_0,t_din_1,sel,t_mux_out);

/*mux_using_assign(
.din_0(t_din_0),
.din_1(t_din_1),
.sel(t_sel),
.mux_out(t_mux_out)

);*/



initial
begin
t_din_0 = 0; t_din_1 = 0; t_sel = 0;

#10
t_sel = 1;


$finish;

end

initial
$monitor($time,,t_mux_out,,t_din_0,,t_din_1,,t_sel);
endmodule

vsim work.test_mux
# vsim work.test_mux
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# ** Warning: t_mux.v(6): [TFMPC] - Too few port connections for 'dut'. Expected 5, found 4.
# Loading work.test_mux(fast)

???????

---------- Post added at 23:43 ---------- Previous post was at 22:51 ----------

then i modified it again

include mux_using_assign.v ;
module test_mux ;

wire mux_out;
reg din_0,din_1,sel;
mux_using_assign dut(din_0,din_1,sel,mux_out);

/*mux_using_assign(
.din_0(t_din_0),
.din_1(t_din_1),
.sel(t_sel),
.mux_out(t_mux_out)

);*/



initial
begin
din_0 = 0; din_1 = 0; sel = 0;

#50
sel = 1;
#100 $stop;

end

initial
$monitor($stime,,mux_out,,din_0,,din_1,,sel);
endmodule

vsim work.test_mux
# vsim work.test_mux
# ** Note: (vsim-3812) Design is being optimized...
# ** Warning: t_mux.v(6): [TFMPC] - Too few port connections for 'dut'. Expected 5, found 4.
# Loading work.test_mux(fast)

the above modification is due to the fact that it is the out put of the blackbox design that we should be analyzing in the waveform viewer, and not the output of the testbench(which essentially is the input to the design under test(hence din_0 etc, the input to the dut are taken as wire and not the usual reg reserved for inputs)

however
1)iam getting this warning
2)modelsim is not printing the signals in object view

1. This is your last port, no comma.
mux_out , // Mux output

2. you are using new version of modelsim. use vsim -novopt test_mux

2) works '
i dont understamd 1) coz there are only 4 prts which i have used

Try to change from

module mux_using_assign(
din_0 , // Mux first input
din_1 , // Mux Second input
sel , // Select input
mux_out , // Mux output

);

to

module mux_using_assign(
din_0 , // Mux first input
din_1 , // Mux Second input
sel , // Select input
mux_out // Mux output

);


The last "," after mux_out can't be there, because if you do, verilog will think you have another empty port after mux_out.

1. First time you haven't mentioned any instance name. So you are getting an error. Later you commented the code and instantiated with an instance name "dut". Now error cleared but warning is reported (See point 2).

2. In mux_using_assign module after mux_out port you have a "," comma. Hence you are getting the warning as "Expected 5, found 4"