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[SOLVED] post synthesize verilog simulation ,TSMC 0.18u standard cells

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hamidmoallemi

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Hi
I am doing my project on "implemetation of wimax FEC processor on 0.18um Cmos"

I have written codes for some of my blocks in verilog and simulated them successfully in Modelsim ,I have synthesized my verilog codes with TSMC 0.18um standard cells using "Cadence PKS_shell" and extracted synthesized verilog code ,
now I want to do post synthesize verilog simulation
but I just have the verilog code,what should I do?
can anyone help me on this

Thanks in advance

Hamid Moallemi
 

With the netlist you got from your synthesis, you can do the "gate-level" simulation. Just vlog your netlist.v and library.v, and with the same test bench you wrote for your RTL, you should be able to run gate-level sims.

After back-end design, you can also do the gate-level sims with sdf file, which contains the delay information. Sdf is obtained from layout tool. The gate level sim with timing provides the most accurate sim you can get in digital sims. It takes longer time, of course.
 
thank you ebuddy
but my problem is library.v from where I can get this?
I use .lef and .tlf files of 0.18um process ,

thank you again
 

Library.v comes from tsmc or its standard cell library vendor (ARM is the one of the standard cell library providers). Since you've already got your .lef and .tlf, I assume you have downloaded the library somewhere. Just go there and look for the verilog model.
 

OK ,
I'll try to find that library
thank you very much ebuddy
 

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