srini.pes
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dc::set_output_delay -clock [find / -clock clk] 0.9 [find / -port OGH2/GH20/DQ10/x_reg[0]/D]
here my clock name is clk and the interested out put port is "OGH2/GH20/DQ10/x_reg[0]/D"..
it showing some error in syntax is it correct or not.........
please guide me
here my clock name is clk and the interested out put port is "OGH2/GH20/DQ10/x_reg[0]/D"..
it showing some error in syntax is it correct or not.........
please guide me