Asking for simple and reliable Ethernet MAC controller

Greetings!
This is my first message here, but I'm reading the forum for some time now, and I'd like to thank you for the work you, guys, are doing here helping each other in the community, and - indirectly - other guys like me from all over the world.

I'm doing my diploma project. It should be a configurable coprocessor for PC. But - shame on me - I ran into a bit if a problem doing Ethernet MAC controller. The problem is I only have a quarter-finished simple controller as a reference. I can finish it, but it will take the kind of time I don't posess. Having realized that I grabbed two controllers from Opencores, but those turned out to be of no use to me: they have wishbone interface (which I don't want), and I can't make heads or tails out of it to eliminate the Wishbone layer. My project hangs in balance.
Thereby, I'm asking you for a simple implementation you could share. I only need 100Base-TX full duplex, i.e. no CSMA/CD.

Thanks in advance.

P.S. Sorry for my English, I'm only learning...

Anyone please? It's a pity to waste so precious time on a work someone had done before...

The opencores implementation isn't bad at all. If you're doing your 'diploma project', you should be quite familiar with VHDL isn't it? Think of it as a project in real life, you're usually on your own too.

If wishbone is your problem, strip it off, it's not that hard to do; or use the Altera implementation.

The other option is this IP stack. I'm not 100% sure it's working fine.

Have fun

lucbra said:

you should be quite familiar with VHDL isn't it?

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Yes, of course. Pretty much.
I tried to strip the wishbone off, but couldn't understand what to do exactly. Probably I should try harder. And there's another downside - that MAC is too huge for my project.
Thank you very much for the links and the advice.

lucbra said:

Have fun

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Oh, I will

Alexium said:

I tried to strip the wishbone off, but couldn't understand what to do exactly. Probably I should try harder. And there's another downside - that MAC is too huge for my project.

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The wishbone interface consumes some logic, but not that much..
Too huge? How small is your FPGA then? The second link could be a smaller alternative, but like I mentioned, I'm not 100% sure of the correct operation.

Stripping the wishbone of means that you will need to replace it with a local bus interface. Don't forget that some of the things of the MAC implementation will need to be called from a processor (internal or external). This local bus will connect to this processor (or microcontroller).

It will still take some time to study the OpenCores implementation. Are you using an evaluation kit from one of the vendors? Maybe they have provided some sort of demonstrator version of a MAC with the kit?

Regards
Luc

lucbra said:

The wishbone interface consumes some logic, but not that much..

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Yes, I know. The logic is consumed by CSMA/CD implementation for half-duplex operation, and I only need full duplex. Probably there are other modules I don't need.
My FPGA is 500k gates. Not too small, but not too big. Opencores' MAC occupies around 40% which leaves me too few space for my project itself. Unfortunately, at the time I don't have money to buy a bigger FPGA board, and free area is crucial as I'm researching reconfigurable coprocessor.

lucbra said:

This local bus will connect to this processor (or microcontroller).

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In my case it will be an FSM that I'll write especially for the occasion and implement in the FPGA.

lucbra said:

Are you using an evaluation kit from one of the vendors? Maybe they have provided some sort of demonstrator version of a MAC with the kit?

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Yes, it's a kit, but they don't provide a MAC implementation. More specifically, they do offer some modules for the Picoblaze - Xilinx's CPU IPcore, but I need a plain HW implementation in order to save resources.

I think I'll take my chances with the second link you gave me, and if it doesn't turn out to be good I'll try to take the opencores implementation and cut the modules I don't need off.

I think I'll take my chances with the second link you gave me, and if it doesn't turn out to be good I'll try to take the opencores implementation and cut the modules I don't need off.

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Seems reasonable. Could you post your results afterwards. It can help others too.
I assume you will run only UDP?

...free area is crucial as I'm researching reconfigurable coprocessor

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I have done something similar with a TigerShark as co-processor. The DSP was connected with the PC using UDP messages. I was very close to 100Mbit transmissing rate. The connection between the PC and the co-processor is usually the bottleneck. You can go much faster when using PCIe x4 or x8. But I assume there is another reason to study this matter (remote processing)...

Good luck,
Luc

lucbra said:

Seems reasonable. Could you post your results afterwards. It can help others too.

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Of course! I also thought about that.

lucbra said:

I assume you will run only UDP?

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Even simpler - I only need the data link layer, i.e. raw Ethernet. Why waste precious bandwidth and FPGA resources on UDP headers?..

lucbra said:

I have done something similar with a TigerShark as co-processor. The DSP was connected with the PC using UDP messages. I was very close to 100Mbit transmissing rate. The connection between the PC and the co-processor is usually the bottleneck. You can go much faster when using PCIe x4 or x8. But I assume there is another reason to study this matter (remote processing)...

Click to expand...

Wow, those DSPs have some impressive specs. I'm afraid my FPGA is no match for such a powerful unit.
I considered many different interfaces - from UART for it's simplicity to PCIEx for it's speed. But I couldn't find any free PCIex controllers at all, nor does my board have appropriate PHY. That's the only reason I chose Ethernet - a compromise between speed, controller complexity and physical support by my board. Besides, if the preoject goes as planned I could connect many boards to one PC - via switch.
Did you manage to get speedup over software implementation?