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They are the timing validation rules for clock signal and reset signal. They just like the setup time and hold time rule for clock signal and reset signal.
recovery and removal times are for asynchronous circuits, what setup and hold are for synchronous circuits. to get a basic introduction on these, digital design by wakerly gives some idea. i'll also see if some other document is there.
Recovery time : -
minimum time that an asynchronous control input pin must be stable before the next active clock edge trasition.
Removal time: - minimum time that an asynchronous control input pin must be stable before being deasserted and after the prvious active clock transition
I have one doubt regarding recovery and removal time. As par as I know we should assert reset asynchronously and de-assert it synchronously, But what happens when the clock edge and reset(usually active low) both are active(i.e clock pos edge and reset is low) at a time? Will it not cause meta stability?
One more doubt is there any chance of having negetive recovery and removal time?
I have one doubt regarding recovery and removal time. As par as I know we should assert reset asynchronously and de-assert it synchronously,
But what happens when the clock edge and reset(usually active low) both are active(i.e clock pos edge and reset is low) at a time? Will it not cause meta stability?
One more doubt is there any chance of having negetive recovery and removal time?
Hi Srini,
Ur assumption of "assert reset asynchronously and de-assert it synchronously" is incorrect..then there is no meaning of asynchronous reset.
Recovery and removal timing checks ensure there is no metastability issue when you come out of reset (low-> high).
Removal Timing Check:
A removal timing check ensures that there is adequate time between an
active clock edge and the release of an asynchronous control signal. The
check ensures that the active clock edge has no effect because the asynchronous
control signal remains active until removal time after the active clock
edge. In other words, the asynchronous control signal is released (becomes
inactive) well after the active clock edge so that the clock edge can have no
effect
Recovery Timing Check:
A recovery timing check ensures that there is a minimum amount of time
between the asynchronous signal becoming inactive and the next active
clock edge. In other words, this check ensures that after the asynchronous
signal becomes inactive, there is adequate time to recover so that the next
active clock edge can be effective. For example, consider the time between
an asynchronous reset becoming inactive and the clock active edge of a
flip-flop. If the active clock edge occurs too soon after the release of reset,
the state of the flip-flop may be unknown.
The definitions you have given for recover and removal time is correct. But what my doubt is nowadays in industry they are using reset synchronizers to avoid metastability problem caused due to asynchrounous de-assertion of reset. Thats what I reported in my previous question.
But what happens when the clock edge and reset(usually active low) both are active(i.e clock pos edge and reset is low) at a time? Will it not cause meta stability?
Thanks,
Srini
QUOTE=chiplogic;831178]Hi Srini,
Ur assumption of "assert reset asynchronously and de-assert it synchronously" is incorrect..then there is no meaning of asynchronous reset.
Recovery and removal timing checks ensure there is no metastability issue when you come out of reset (low-> high).
Removal Timing Check:
A removal timing check ensures that there is adequate time between an
active clock edge and the release of an asynchronous control signal. The
check ensures that the active clock edge has no effect because the asynchronous
control signal remains active until removal time after the active clock
edge. In other words, the asynchronous control signal is released (becomes
inactive) well after the active clock edge so that the clock edge can have no
effect
Recovery Timing Check:
A recovery timing check ensures that there is a minimum amount of time
between the asynchronous signal becoming inactive and the next active
clock edge. In other words, this check ensures that after the asynchronous
signal becomes inactive, there is adequate time to recover so that the next
active clock edge can be effective. For example, consider the time between
an asynchronous reset becoming inactive and the clock active edge of a
flip-flop. If the active clock edge occurs too soon after the release of reset,
the state of the flip-flop may be unknown.[/QUOTE]
Hi Srini,
"
The definitions you have given for recover and removal time is correct. But what my doubt is nowadays in industry they are using reset synchronizers to avoid metastability problem caused due to asynchrounous de-assertion of reset. Thats what I reported in my previous question. "
I agree that using reset synchronizers is also good option...i do see reset synchronizers in our designs especially when reset is generated in different clock domain than source domain.
I dont think there is metastability issue while asserting reset . Because reset is asynchronous.
Say if both active clock edge and reset comes at same time..reset dominates after some time where active edge will not be there..so in case of assertion of asynchronous reset there is no metastability issue.
Then what's the point of defining recovery time and why should we check for recovery time?
What is the significance of recovery time in digital circuits?
Then what's the point of defining recovery time and why should we check for recovery time?
What is the significance of recovery time in digital circuits?
Recovery time/removal time are needed for de-assertion of reset...because when you de-assert the reset the next active clock edge should capture D input properly..
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