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An IRQ is an electrical signal generated by a device needing attention. Usually, it means that some event has occurred such as data being received and ready to use. The IRQ signal is sometimes connected directly to the processor or in some cases to a dedicated interrupt handling circuit. When the processor is told the interrupt has happened it calls the ISR to handle it.
The ISR is software that deals with the needs of the device that requested it. Usually, the device is read or some system action is taken to clear the condition that caused the IRQ then the interupt system is reset to make it ready for use again.
On most systems, the IRQ signal forces the processor to save it's current program counter so it knows where to return when the ISR is finished, then it jumps to a hard-wired address called the Interrupt Vector where the code for the ISR is placed. At the end of the ISR, the program counter is restored and the program carries on from where it was before the interrupt paused it.
The IRQ is an electrical signal that triggers the ISR as soon as it happens, no matter what the program is doing at the time. It is an immediate request for action that works with the processor hardware to make it jump to the service routine. You are thinking of a polled interrupt system where the software periodically checks to see if a device is requesting attention.
Vectored IRQs have the middle priority, but ony 16 of the 32 requests can be assigned to this category. Any of the 32 requests
can be assigned to any of the 16 vectored IRQ slots, among which slot 0 has the highest priority and slot 15 has the lowest.
Non-vectored IRQs have the lowest priority.
The VIC ORs the requests from all the vectored and non-vectored IRQs to produce the IRQ signal to the ARM processor. The
IRQ service routine can start by reading a register from the VIC and jumping there. If any of the vectored IRQs are requesting,
the VIC provides the address of the highest-priority requesting IRQs service routine, otherwise it provides the address of a default
routine that is shared by all the non-vectored IRQs. The default routine can read another VIC register to see what IRQs are active.
Ckshivaram, your details may be correct for one specific type of device but the original poster has not told us anything abut the hardware at all except that it is an embedded system.
The vast majority of embedded systems do not use an interrupt controller, let alone one with a priority encoder. Your answer is only applicable to some ARM based computers.
As ckshivaram states, GPS is serial data and that has nothing at all to do with the mechanics of IRQs.
I'm guessing what you want to do is feed the data to a UART input and have the UART generate an IRQ when a full byte has been received. The IRQ could then be used to alert your processor that the byte is ready to be picked up before it gets overwritten by the next one arriving from the GPS. Remember that serial data is just a sequence of 1s and 0s, the UART has the job of working out where one group of 8 (1 byte) starts and finishes within the stream of bits it sees from the GPS.
If I'm correct, you need to configure the UART to generate the IRQ and in the processor software you need to write an ISR that reads the UARTs received data register and stores the byte somewhere until the full GPS message has been assembled.
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