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assign signal to variable

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mohammadyou

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hi all

In my project, i have to assign signal to variables !
how can i done this. assign signal to variable and inverse ?

and have i permitted to declare process into generate block ?:shock:
if i want to declare sequential design into generate block
what should i do

thank you
yousefi
 

i appreciate you

i have a mistake because i assign signal to variable and i think i must use <= (error:Signal "a" cannot be target of variable assignment statement)

and have i permitted to declare process into generate block (because in generate block i should use concurrent assignment) ?
i want to create concurrent statement that have sensitive list :!:
and what can i do ?

thanks
 
Last edited:

I'm sorry but i have never used blocks in VHDL
I searched using google, i found two guides

VHDL Concurrent Statements
VHDL Reference Guide - Block Statement

Is your project just for simulation or should it be synthesized, in the second link it says

Without a guard condition a block is a grouping together of concurrent statements within an architecture. It may have local signals, constants etc. declared.
IF an optional guard condition is included, the block becomes a guarded block. the guard condition must return a boolean value, and controls guarded signal assignments within the block. If the guard condition evaluates to false, the drive to any guarded signals from the block is "switched off"
and
Unguarded block statements are usually ignored by logic synthesis tools (i.i. all blocks within an architecture are "flattened").
Guarded block statements are not usually supported for synthesis.

Sequential (i.e. flip-flop and register) behaviour can be modelled using guarded blocks, but again for synthesis and readability it is better described using "clocked" processes.

so it actually says that guarded blocks can not be synthesized and recommends to use processes.

Alex
 

thank for your help

i should to synthesis my project :sad::sad::sad:
 

I don't exactly understand your problem. You should better give a code example (no matter if it has syntax errors) to clarify your intention.

Your assumption, that you can't place a process in a generate block is however wrong. You can have any concurrent code, including component instantances and also sequential blocks.

As an example:
Code: 
FOR I IN 0 TO 15 GENERATE
PROCESS(clk) 
BEGIN
   IF rising_edge(clk) THEN 
      c(i) <= a(i);
   END IF;
END PROCESS; 
END GENERATE;
 

my_sig <= other_sig + my_variable + my_function(my_const, my_variable); -- as long as other_sig, my_variable, and the return type of my_function are all compatible (and "+" is defined for that type), the above will work. It will perform a non-blocking assignment.

my_variable := my_sig + other_variable + my_function(my_const, my_variable); -- same thing. As long as all of the types are correct, and all operators defined, this will work. In this case, a blocking assign is performed.

sig <= '0';
sig <= sig;
The above code results in the sig <= '0' line being ignored. The non-blocking assign means sig is not updated until after all processes have been evaluated. The last non-blocking assignment to sig is "sig <= sig;".

var := '0';
var := var;
This code would evaluate the var := '0'; line first. Then it would evaluate var := var; Thus at the end of the process, var will have a value of 0.

In verilog, the user is free to use blocking/non-blocking assigns on anything. This leads to issues, as blocking assigns update immediately and verilog doesn't enforce any evaluation order of its processes. VHDL solves this problem by forcing variables to be local to the process and preventing signals from using blocking assignments. VHDL made a mistake in that variables cannot use non-blocking assigns and can only use blocking assigns. This has led to some style guides recommending that only signals be used, as the behavior is easier to predict, and less error prone. Using local variables actually does improve simulation time.
 

FvM said:
I don't exactly understand your problem. You should better give a code example (no matter if it has syntax errors) to clarify your intention.

Your assumption, that you can't place a process in a generate block is however wrong. You can have any concurrent code, including component instantances and also sequential blocks.

As an example:
Code: 
FOR I IN 0 TO 15 GENERATE
PROCESS(clk) 
BEGIN
   IF rising_edge(clk) THEN 
      c(i) <= a(i);
   END IF;
END PROCESS; 
END GENERATE;
Click to expand...

i wrote this code
Code: 
  Build_NN_Layer1: for i in 0 to Layer_Perceptron generate
                          Net_Layer(i) <= (Pixel_1*W1(i,0)+b1(i)
                                          +Pixel_2*W1(i,1)+b1(i)
                                          +Pixel_3*W1(i,2)+b1(i)
                                          +Pixel_3*W1(i,2)+b1(i)
                                          +Pixel_4*W1(i,3)+b1(i)
                                          +Pixel_5*W1(i,4)+b1(i)
                                          +Pixel_6*W1(i,5)+b1(i)
                                          +Pixel_7*W1(i,5)+b1(i)
                                          +Pixel_8*W1(i,7)+b1(i)
                                          +Pixel_9*W1(i,8)+b1(i));
                           Process (Net_Layer(i)) is
                           begin
                              SF: Sigmoid_Function port map (Net => Net_Layer(i),Output => Output_Layer(i));  
                           end process; 
                    end generate;

in modelsim i have this error
vhd(113): Illegal sequential statement. for line "SF: Sigmoid_Function port map (Net => Net_Layer(i),Output => Output_Layer(i));"

1)i have two concurrent statement that i want one statement execute after other statement [if i could use guarded block in synthesis, my problem solved]

2) when i change my sensitivity list to (Net_Layer(i)'event) i have this error : vhd(111): Expression is not a signal.

thank you so much
and i apologize for my English
 

component instantiation isn't done inside processes. the instance can be placed outside of the process. eg:
Code: 
 g_example : for ii in 1 downto 0 generate
begin
  u_example : component example port map(X => x(i), Y => y(1-i), Z => z);
end generate;

which will instantiate two components, g_example.0/u_example, and g_example.1/u_example. if names are important for your UCF file, note that some synthesizers will number the instances from 0 instead of using the generate variable. eg, the component connected to x(1) would be named .0 because it was the first to be elaborated. likewise the component connected to x(0) would be .1, as it was the second elaborated. In most cases, it isn't important.
 

permute said:
component instantiation isn't done inside processes. the instance can be placed outside of the process. eg:
Code: 
 g_example : for ii in 1 downto 0 generate
begin
  u_example : component example port map(X => x(i), Y => y(1-i), Z => z);
end generate;

.
Click to expand...

ok but how can i insert condition to my concurrent statement for example
i want create this
Code: 
  Build_NN_Layer1: for i in 0 to Layer_Perceptron generate
                          Net_Layer(i) <= (Pixel_1*W1(i,0)+b1(i)
                                          +Pixel_2*W1(i,1)+b1(i)
                                          +Pixel_3*W1(i,2)+b1(i)
                                          +Pixel_3*W1(i,2)+b1(i)
                                          +Pixel_4*W1(i,3)+b1(i)
                                          +Pixel_5*W1(i,4)+b1(i)
                                          +Pixel_6*W1(i,5)+b1(i)
                                          +Pixel_7*W1(i,5)+b1(i)
                                          +Pixel_8*W1(i,7)+b1(i)
                                          +Pixel_9*W1(i,8)+b1(i));
                    end generate;

and after that for next stage (Output Of Net_layer(i)) i have

Code: 
  Build_NN_SF: for i in 0 to Layer_Perceptron generate        
                              SF: Sigmoid_Function port map (Net => Net_Layer(i),Output => Output_Layer(i));   
                    end generate;

i must insert condition for Build_NN_SF, that i sure this statement place in output of Net_Layer(i) and sensitive to Net_Layer(i) ??:-?

Thanks :idea:
 
Last edited:

i must insert condition for Build_NN_SF, that i sure this statement place in output of Net_Layer(i) and sensitive to Net_Layer(i) ??
Click to expand...
Instantiating a component means, that it "executed" unconditionally. You can't make it depend on any condition. A component is like a block of logic hardware in a circuit with input and output wires. You can't decide to have it in the circuit for one clock cycle and bypass for the other. If you want to make it's operation depend on additional conditions, you have to add an enable signal to the component definition, that is set according to your intentions.

You should also consider, that process sensitivity lists are ignored in synthesis execpt for edge sensitive events.
 
thank you for you explanation,

if i write my code like this
Code: 
  Build_NN_Layer1: for i in 0 to Layer_Perceptron generate
                          Net_Layer(i) <= (Pixel_1*W1(i,0)+b1(i)
                                          +Pixel_2*W1(i,1)+b1(i)
                                          +Pixel_3*W1(i,2)+b1(i)
                                          +Pixel_3*W1(i,2)+b1(i)
                                          +Pixel_4*W1(i,3)+b1(i)
                                          +Pixel_5*W1(i,4)+b1(i)
                                          +Pixel_6*W1(i,5)+b1(i)
                                          +Pixel_7*W1(i,5)+b1(i)
                                          +Pixel_8*W1(i,7)+b1(i)
                                          +Pixel_9*W1(i,8)+b1(i));
   
                              SF: Sigmoid_Function port map (Net => Net_Layer(i),Output => Output_Layer(i));  
 
                    end generate;
means, i wrote concurrent statement, sigmoid_function that drived with Net_Layer
when i synthesize this code in ise i have warning :

"WARNING:Xst:524 - All outputs of the instance <Build_NN_Layer1[12].SF> of the block <Sigmoid_Function> are unconnected in block <Best_NN>.
This instance will be removed from the design along with all underlying logic"

for each iteration of generation this warning show
where is my problem?!!
 

SF: Sigmoid_Function port map (Net => Net_Layer(i),Output => Output_Layer(i));
Click to expand...

You connect all 9 Net_Layer to Net and all 9 Output_Layer to Output,
Where do you define the net and output?
What is the bit length of it?

Alex

---------- Post added at 16:21 ---------- Previous post was at 16:12 ----------

Also in some point you have to assign the logic you created to an actual physical port (of the chip), anything that is not used is removed.

Alex
 

here is my Signal type
Code: 
Pixel_1 : in  STD_LOGIC_VECTOR (15 downto 0);
all Pixel Same as this

Code: 
generic (Layer_Perceptron : integer := 12);

type Bound_Net is array (0 to Layer_Perceptron) of STD_LOGIC_VECTOR (15 downto 0);
signal Net_Layer: Bound_Net; 
signal Output_Layer:Bound_Net;

and in component i have
Code: 
    Port ( Net : in  STD_LOGIC_VECTOR (15 downto 0);
           Output : out  STD_LOGIC_VECTOR (15 downto 0));

i connect in every iteration one Net_Layer to Net and then result put in Output_Layer
 

thank you so much8-O
i forgot assign output_layer :oops:

very helpful:-D

have good time.
 

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