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An exact multiply of arbitrary input frequncies isn't feasible by "all-digital" methods. You always need an analog VCO component. Referring to discrete time domain, a DPLL or ADPLL (all digital PLL) can do, but the generated output frequency will be sampled at discrete times, according to a system clock.
Hi, you have two clock edges, as such you can create a clock doubler using delays. This is not synchronous, the pulse width is not fixed, and it is just bad design...but you can do it. You need to bypass this logic for DFT and be sure your best-case timing results still provide a pulse width that is acceptable.
In my understanding, a delay line, strictly spoken even a logic gate delay chain, is an analog component.
You may also take a look at the "digtal" PLL method described in the below link:
In my understanding, it's not strictly digital, but it works with only digital gates, without the voltage controlled ring oscillators usually utilized for VCOs.
I had worked on DPLL using spice. Now, I thought it was easy to model a ADPLL using the same knowledge.
I had successfully implemented all the other blocks. But, I understood that implementing a DCO using the ring oscillator methodology (set of inverter chains whose enable is controlled by the output of binary to thermometer decoder) is impossible in VHDL.
I did have a top level look at PLL book written by Roland. E Best.
I guess i might have to spend more time to really understand it. My Analog PLL knowledge does not seems to be sufficient to model the ADPLL
The described ADPLL based on a programmable ring oscillator is using the same method as the below linked "C3-PLL". Chip cologne has however improved the PLL behaviour by adding a first order SD-modulator (a "PWM").
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