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ByteblasterMV pcb board

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alexan_e

alexan_e

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Hi
I bought a few MAXII cpld from altera and i needed a programmer so i designed a pcb for byteblasterMV because i couldn't find a ready (pcb), i have made both a dip and smd version (for 74HC244 only, other components are not smd), both single layer.
The schematic i have used is from the Altera datasheet, but i have changed the input output pins to the board , this pcb is intended to be used with a cable about 1m from the parallel port and short jtag cables to the chip (board will be near the chip).
I'm a hobbyist so this are not professional boards but they do what i need.
I have attached the schematic, layout, and pcd for both versions

Alex
 

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  • byteblastermv_rev2.zip
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Hi,
I am a newbie in cpld and FPGA. So I have some questions I would like to know.
When you use jtag to program a MAXII CPLD, what happened when you turn off the power. All the program was still on chip or it was volatile.

Is it ok if I program with pof file using quartus II v8.01.

Regards,

P/S: because I have a first project to work with CPLD so that I feel really difficult, please help me.
 

Hi

check About Programming
During compilation, the Compiler automatically generates an SRAM Object File (.sof) or a Programmer Object File (.pof) for the target device. You can use SRAM Object Files to configure all Altera FPGA devices supported by the Quartus II software. You can use Programmer Object Files to program all Altera CPLD devices supported by the Quartus II software.

You can also read but note my pcb has the input/output pins in different order but functionality is still the same.

CPLD's have internal memory that holds the program files if they are turned off, FPGA's need to be programed every time they are turned on

Alex
 
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