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Quartus II inout pin as o/p only..problem.

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jimmy_tag

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I got the following warnings when i compiled my design

Warning: Inserted always-enabled tri-state buffer between "DA[0]" and its non-tri-state driver.

Info: Pin DA[0] has a permanently enabled output enable

I didnt understood whats the meaning of the warning, but only understood that it is enabled as o/p pin only. how can i configure a pin as both i/p and o/p...?? is there any other way else than 'inout'..?

Also what is the diffrence between 'buffer' and 'inout'?
 

You provided an inout signal in the top entities port, but are driving it as an output only. It's not an error, the compiler just reported how your design operates. If you intend something different, edit your design.

A VHDL "buffer" is an output pin that can be read back internally. But is still an output, it can't read external signals.
 

Actually, I am developing an interface for SRAM so as I want 8 bit inout pins for data-in and data-out.I designed State machine in VHDL code and compiled it and then synthesized. for o/p i used 8 leds so that i can get o/p as 8 bit no. from 0 to 255. i was succefful in writing data.. i.e. using the data pins for o/p, but i am unable to read them as input so my read operation is not working, can it be code problem??
 

yes, if you check the synthesis reports, you'll usually see some reason why. It usually starts very vague, with lines like "unreachable state" or "register output unused" or "register always 0, removing". In your case, I'll suggest the obvious -- do you ever tri-state the outputs? if you drive the lines to '0' instead of 'z', the other end of the bus will not be able to drive the lines properly, and you will (almost certainly) receive all '0's.
 

in vhdl you can only configure the port bidirectional by 'inout'...

but while using inout you had to make the tristated i.e. o/p as 'Z' state which will be only enabled by the i/p device or o/p device gives enable signal..

for buffer and inout diffrence check the below link:

VHDL answers to frequently asked ... - Google Books
 

You have to use a flag to set the pin as input or output, i use the following way

Code: 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity in_out_test is
  port ( clk: in std_logic;
	   pin_mode: in std_logic;  -- 0=in   1=out
	   in_out: inout std_logic:='Z');

end in_out_test;

architecture Behavioral of in_out_test is
	signal in_out_buffer: std_logic:='0';
begin
 
process (clk)

 begin
	
	if (clk'event and clk='1') then		
		         
		if (pin_mode='1') then	-- pin is output
		                      -- you can also write this value in advance (while pin_mode=0) since it is a buffer 
                                      -- and when the pin becomes an output the buffer value will be transferred to output
			in_out_buffer <= write_this_value_to_pin;
		
		else  -- pin is input		
		
			read_the_value <= in_out;
		
		end if;
		
	end if;
		
end process;

-- tristate for in_out
in_out <= in_out_buffer when (pin_mode=1)	-- output
else (others => 'Z');				--input

end Behavioral;

Alex
 
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