hobbss
Member level 2
I am working on a design and can't get my vias to work correctly.
First, a general question:
If I want to have a via just for signaling purposes, i.e., not to be "probe-able," is there any reason why I should not cover it with soldermask at both ends (something about "de-gassing"?)? I believe this is called a "tented" via (is this correct?), and to do design it, in my padstack editor, I created a pad with a 10mil drill hole, a 30/40/40 mil pad/thermal/antipad for begin, internal, and end layer, and then left the soldermask top and soldermask bottom layers as nulls. Will this create a throughhole via that is covered with soldermask at both ends?
Second, an OrCAD specific question:
I have created a four layer board -- top and bottom are signal layers. Layers 2 & 3 are plane layers. I used the SETUP --> OUTLINES --> PLANE OUTLINES to create shapes bounded by the board outlines, and assigned nets to the two planes (+5V and GND). I then placed a test component on the board, and attempted to route the ground pins by fanning out a trace and dropping a via. The problem is that the via seems to be grabbing both planes. The worst/most confusing part is that the software doesn't like that the vias are grabbing ANY planes. Meaning, I get two DRC errors for each via -- "Shape to Thru Via Spacing" for both planes. Interestingly enough, the test part is a SMD with a thermal ground pad underneath it. I designed the thermal ground pad to have a grid of four holes in it --> nominally to grab a ground plane to dissipate more heat. I am only getting one DRC error for this pad (complaining that it is too close to the +5V plane).
Extra information:
1. From the layout, it looks like there is no thermal relief (or antipads) on the vias at all -- i.e., they are buried in the planes. Would I only be able to see the antipads/thermal relief in actual gerbers, or should I be able to see them in the pcb editor?
2. I defined the via padstack to have a drill size of 10mils, with a pad size of 30 mils, and anti-pad and thermal relief of 40 mils each -- all circular (On a side note, I thought that thermal relief was only for holes that would have pins in them, but the software complains if I try to have an anti-pad and no thermal relief. What am I missing here?).
3. As an additional test, I ran a signal wire from the top layer, through a via, across the bottom layer, back through a via, and connected it to its destination pin. However, both signal vias grabbed both internal plane layers (the same as the ground and power
vias described above).
I must be missing something simple about either planes, vias, or both. Any advice would be appreciated.
On a side note, is it possible to make pin numbers invisible in PCB Editor? I have a small component with 16 pins, and the pin numbers are > 3 times the size of the pins. It makes the drawing really cluttered with all the pin numbers there.
First, a general question:
If I want to have a via just for signaling purposes, i.e., not to be "probe-able," is there any reason why I should not cover it with soldermask at both ends (something about "de-gassing"?)? I believe this is called a "tented" via (is this correct?), and to do design it, in my padstack editor, I created a pad with a 10mil drill hole, a 30/40/40 mil pad/thermal/antipad for begin, internal, and end layer, and then left the soldermask top and soldermask bottom layers as nulls. Will this create a throughhole via that is covered with soldermask at both ends?
Second, an OrCAD specific question:
I have created a four layer board -- top and bottom are signal layers. Layers 2 & 3 are plane layers. I used the SETUP --> OUTLINES --> PLANE OUTLINES to create shapes bounded by the board outlines, and assigned nets to the two planes (+5V and GND). I then placed a test component on the board, and attempted to route the ground pins by fanning out a trace and dropping a via. The problem is that the via seems to be grabbing both planes. The worst/most confusing part is that the software doesn't like that the vias are grabbing ANY planes. Meaning, I get two DRC errors for each via -- "Shape to Thru Via Spacing" for both planes. Interestingly enough, the test part is a SMD with a thermal ground pad underneath it. I designed the thermal ground pad to have a grid of four holes in it --> nominally to grab a ground plane to dissipate more heat. I am only getting one DRC error for this pad (complaining that it is too close to the +5V plane).
Extra information:
1. From the layout, it looks like there is no thermal relief (or antipads) on the vias at all -- i.e., they are buried in the planes. Would I only be able to see the antipads/thermal relief in actual gerbers, or should I be able to see them in the pcb editor?
2. I defined the via padstack to have a drill size of 10mils, with a pad size of 30 mils, and anti-pad and thermal relief of 40 mils each -- all circular (On a side note, I thought that thermal relief was only for holes that would have pins in them, but the software complains if I try to have an anti-pad and no thermal relief. What am I missing here?).
3. As an additional test, I ran a signal wire from the top layer, through a via, across the bottom layer, back through a via, and connected it to its destination pin. However, both signal vias grabbed both internal plane layers (the same as the ground and power
vias described above).
I must be missing something simple about either planes, vias, or both. Any advice would be appreciated.
On a side note, is it possible to make pin numbers invisible in PCB Editor? I have a small component with 16 pins, and the pin numbers are > 3 times the size of the pins. It makes the drawing really cluttered with all the pin numbers there.
