Pass through every 10th pulse

eladla · Sep 27, 2010

Hi!

I`m trying to create a counter that will count nine rising edges of the input clock and do nothing and then on the 10th rising edge output a pulse until the input clock goes back low and then begin counting again, i.e. I want to pass every 10th clock pulse and the input pulse length is variable. I got something going, but I used a while loop and it seems not to be synthesizer friendly. Syplify keeps asking me to raise the loop limit, but since it`s a while, I can`t know the loop limit ahead of time. I`m guessing there is a better way to do this, I`m just new to Verilog.

Please help!
Thank you.

Code:

`timescale 1 ns / 100 ps


module pulse_generator (pulse_in, pulse_out);


input pulse_in;
output pulse_out;
reg [8:0] Counter;
reg pulse_out;

always @ (posedge pulse_in)
begin


Counter <= Counter + 9'h1;
if(Counter == 9'b111111111)
begin
    // synthesis loop_limit 8000
    while (pulse_in == 1'b1) begin
        pulse_out <= pulse_in;
    end
    Counter <= 9'b000000000;
end
end

endmodule

---------- Post added at 06:06 ---------- Previous post was at 05:39 ----------

Well... I have made some progress, but still having synthesis issues.

Code:

module pulse_generator (pulse_in, pulse_out);


input pulse_in;
output pulse_out;
wire pulse_in;
reg [3:0] Counter;
reg pulse_out;

initial
    begin
    Counter = 4'd0;
    pulse_out = 0;
    end

always @ (posedge pulse_in)
begin


Counter = Counter + 1;
if(Counter == 4'd9)
begin
    pulse_out = pulse_in;
    @(negedge pulse_in)
    pulse_out = 1'b0;
    Counter = 4'd0;
end
end

endmodule

Now Synplify tells me I can`t use posedge and negedge of pulse_in in the same always block. I don`t get why this is a hardware limitation, but ok...

Any other way to do this?

shitansh · Sep 27, 2010

Where is input clock in code? Still your question is not clear. Try to put wave form here and proper question.

eladla · Sep 27, 2010

The input clock is in the stimulus file.
It`s:
"#10 pulse_in = ~pulse_in;"

I want every 10th pulse to show up at the output,
and I want the pulse at the output to be the same size as the pulse in the input.

I hope it`s clearer now.

lostinxlation · Sep 27, 2010

Does this work ?

Code:

always @ (posedge pulse or negedge reset_n) begin
  if(!reset_n)  cnt <= 4'b0;
  else if (cnt == 4'd9) cnt <=4'b0;
  else cnt <= cnt + 1;
end

assign out = pulse & ~(|cnt[3:0]) ;

If you implement this with the real circuit, you need to make sure that pulse reaches the final AND gate later than ~|cnt[3:0], otherwise you'll get a glitch on the output.

eladla · Sep 27, 2010

Thanks!
I`m new to Verilog (been doing analog for a long time).
The assign statment was what I was looking for.
I was thinking: "There must be a statment that "connects" a wire to some changing value, like when a latch becomes transparent"
Guess that was it

---------- Post added at 10:16 ---------- Previous post was at 09:02 ----------

I just synthesized the circuit and added two inverters (three in total) to the pulse going in to the last NAND.
It does make the glitch go away,
but it also makes the pulse longer, i.e. it doesn`t go low and back (glitch), it just remaines high.
I need the pulse to be the length of the input pulse (not it`s double).

Any ideas?
Thanks!

---------- Post added at 10:46 ---------- Previous post was at 10:16 ----------

NM. Got it working.
I didn`t need to only delay it,
I had to sync the delayed and undelayed duety cycles.
Thanks again!

shitansh · Sep 27, 2010

eladla said:
The input clock is in the stimulus file.
It`s:
"#10 pulse_in = ~pulse_in;"

I want every 10th pulse to show up at the output,
and I want the pulse at the output to be the same size as the pulse in the input.

I hope it`s clearer now.

Try below code

Code:

`timescale 1ns/100ps
module top
(
   input  wire         pulse_in
  ,input  wire         reset_n
  ,output wire         pulse_out
);

  reg  [03:00] count, count_2;
  reg          pulse_1, pulse_2;

  always @ (posedge pulse_in or negedge reset_n)
    begin
      if (~reset_n)
        begin
          count <= {4{1'b0}};
        end
      else
        begin
          if (count == 4'h9)
            count <= {4{1'b0}};
          else
            count <= count + 1'b1;
        end
    end

  always @ (posedge pulse_in or negedge reset_n)
    begin
      if (~reset_n)
        begin
          pulse_1 <= 1'b0;
        end
      else
        begin
          if (count == 4'h9)
            pulse_1 <= 1'b1;
          else
            pulse_1 <= 1'b0;
        end
    end

  always @ (negedge pulse_in or negedge reset_n)
    begin
      if (~reset_n)
        begin
          count_2 <= {4{1'b0}};
        end
      else
        begin
          count_2 <= count;
        end
    end

  always @ (negedge pulse_in or negedge reset_n)
    begin
      if (~reset_n)
        begin
          pulse_2 <= 1'b0;
        end
      else
        begin
          if (count_2 == 4'h9)
            pulse_2 <= 1'b1;
          else
            pulse_2 <= 1'b0;
        end
    end

assign pulse_out = ( (pulse_1) && (~pulse_2) );

endmodule

here is its testbench

Code:

`timescale 1ns/100ps

module top_tb();

  reg          clock, reset_n;
  wire         pulse_out;
  top top_instance
    (
      .pulse_in  ( clock     ), // input 
      .reset_n   ( reset_n   ), // input
      .pulse_out ( pulse_out )  // output
    );

  initial
    begin
      clock = 1'b0;
      reset_n = 1'b1;
    #15
      reset_n = 1'b0;
    #15
      reset_n = 1'b1;
    #1000
      $stop;
    end

  always 
    begin
      #5 clock = !clock;
    end
endmodule

Advantage is there will not any glitch on output. And code is synthesized properly

HTH

eladla · Sep 27, 2010

Thank you!
This also works, but the it amounts to a much larger layout.
Since lostinxlation`s solution works, I think it`s a better fit for me.
Thanks for your effort.

shitansh · Sep 28, 2010

eladla said:
Thank you!
This also works, but the it amounts to a much larger layout.

If you concern about area then try below code consume same resources only one negedge D-flipflop is more. You will not see any glitch here in simulation or in hardware.

Code:

`timescale 1ns/100ps
module top
(
   input  wire         pulse_in
  ,input  wire         reset_n
  ,output wire         pulse_out
);

  reg  [03:00] count;
  reg          pulse_1, pulse_2;

  always @ (posedge pulse_in or negedge reset_n)
    begin
      if (~reset_n)
        begin
          count <= {4{1'b0}};
        end
      else
        begin
          if (count == 4'h9)
            count <= {4{1'b0}};
          else
            count <= count + 1'b1;
        end
    end

  always @ (posedge pulse_in or negedge reset_n)
    begin
      if (~reset_n)
        begin
          pulse_1 <= 1'b0;
        end
      else
        begin
          if (count == 4'h9)
            pulse_1 <= 1'b1;
          else
            pulse_1 <= 1'b0;
        end
    end

  always @ (negedge pulse_in or negedge reset_n)
    begin
      if (~reset_n)
        begin
          pulse_2 <= 1'b0;
        end
      else
        begin
          pulse_2 <= pulse_1;
        end
    end

assign pulse_out = ( (pulse_1) && (~pulse_2) );

endmodule

eladla said:
Since lostinxlation`s solution works, I think it`s a better fit for me.

If you only concern for simulation then it lostinxlaton's solution will work where you need to play with delay to take care for glitch, but if you wanted to implement on hardware then glith will be there and on hardware to play with delay is bit tricky.

Welcome to EDAboard.com

Pass through every 10th pulse

eladla

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