Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

How to wait for a fixed time in one state or loop in VHDL?

Status
Not open for further replies.

akshay.dhanawade

Newbie level 3
Joined
Aug 12, 2010
Messages
3
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Location
India
Activity points
1,297
is the wait statement synthesized if not then how i can wait for some fixed time in one state or loop? is there any option?
 

Re: delay in vhdl

The wait statement is used to wait in a particular loop but it is not synthesized as in real time in hardware there in no wait state.
Use a counter equal to the time you want the wait statement to execute. Keep on incrementing the counter and write a if loop or a condition that unless your counter is reached specified value be in loop.
 
Re: delay in vhdl

you can use counter or shift registers or you can use mux logic like

if (signal_active)
...............
else
..................
 

Re: delay in vhdl

the wait statement can be synthesized as follows but only one time in process as follows:

wait until rising_edge(clk);


for delay you have to use clock divider, which divides the on-board clock freq say 24MHz to you required frequency say 1KHz generating clock pulse with 1ms time period(delay) .

You can use the code synthesized by me on my blog. it is completely synthesizable.

https://jimmy-embedded-c-n-vhdl.blogspot.com/
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top