What is a 'deep depletion'?

deep depletion...

could you explain it really really as in easy as even a child may understand?

Look at Fig. 4.4. (C-V characteristic of a poly/n-well MOSCAP) in the PDF below. The deep depletion region is the range in the depletion region, where the low frequency CV curve is at (or close to) its minimum, or - in short form - the center part of the depletion region.

At the min. value of the CV curve (in the center of the depletion region), the Vg voltage not only compensates the fixed positive charges of the n dopant ions, but also has driven away all the mobile negative charges (the electrons) and so created a wide space charge region (hence the CV curve is at its minimum value). Further lowering the Vg voltage (to more negative values) starts to generate mobile positive charges (holes) at the Si/SiO2 interface, which penetrate into the depletion region and so increase the MOSCAP's capacitance, until full inversion takes place and the MOSCAP reaches its maximum capacitance Cmax = ε/tox . This is well detailed in the PDF below.

I'm not sure if your child will understand this ;-)

erikl said:

Look at Fig. 4.4. (C-V characteristic of a poly/n-well MOSCAP) in the PDF below. The deep depletion region is the range in the depletion region, where the low frequency CV curve is at (or close to) its minimum, or - in short form - the center part of the depletion region.

At the min. value of the CV curve (in the center of the depletion region), the Vg voltage not only compensates the fixed positive charges of the n dopant ions, but also has driven away all the mobile negative charges (the electrons) and so created a wide space charge region (hence the CV curve is at its minimum value). Further lowering the Vg voltage (to more negative values) starts to generate mobile positive charges (holes) at the Si/SiO2 interface, which penetrate into the depletion region and so increase the MOSCAP's capacitance, until full inversion takes place and the MOSCAP reaches its maximum capacitance Cmax = ε/tox . This is well detailed in the PDF below.

I'm not sure if your child will understand this ;-)

Click to expand...

Erik - your picture 4.4 does not show a deep depletion. It shows just the "usual" (low-frequency, or steady-state) depletion.

If we have an MOS capacitor on a p-type substrate, and if there is no n+ region connected to a voltage source that can provide instantaneously a supply of electrons, and if we sweep the gate voltage from negative value (corresponding to accumulation regime) to positive value very fast - faster than the thermal generation lifetime - then the depletion region will extend way beyond the "steady-state" or usual depletion. After some time of waiting (longer than the thermal generation lifetime), electrons will be generated in the depletion region and attracted to the oxide and form an inversion layer and screen the gate voltage - the depletion region then will become thinner and will correspond to steady-state or DC depletion region.

Max
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timof said:

If we have an MOS capacitor on a p-type substrate, and if there is no n+ region connected to a voltage source that can provide instantaneously a supply of electrons, and if we sweep the gate voltage from negative value (corresponding to accumulation regime) to positive value very fast - faster than the thermal generation lifetime - then the depletion region will extend way beyond the "steady-state" or usual depletion. After some time of waiting (longer than the thermal generation lifetime), electrons will be generated in the depletion region and attracted to the oxide and form an inversion layer and screen the gate voltage - the depletion region then will become thinner and will correspond to steady-state or DC depletion region.

Max
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Click to expand...

I guess you're right, Max, it's a purely dynamic phenomenon, thanks for the correction!
I forgot that deep depletion can only be achieved by a dynamic voltage slew rate which overtakes the charge generation time, when no charge injection from an adjacent junction is possible.

If such a dynamic state is generated by a MOS capacitance (I think it is also possible with a reverse-operated (PIN) diode), there's probably a practical limitation on the substrate's doping concentration: the space charge region's thickness must be large enough to take over the lion's share of the voltage in order to save the MOS oxide from breakthrough, and so with the unfavorable dielectric constant ratio of 3 between Si and SiO2. I.e. with a MOSCAP, deep depletion can only be achieved on a lowly doped substrate; at a high doping concentration, the MOS oxide is likely to (destructively) break through before deep depletion can be achieved, I guess.

Pls. tell me, if you think I'm wrong again!

erikl said:

I guess you're right, Max, it's a purely dynamic phenomenon, thanks for the correction!
I forgot that deep depletion can only be achieved by a dynamic voltage slew rate which overtakes the charge generation time, when no charge injection from an adjacent junction is possible.

If such a dynamic state is generated by a MOS capacitance (I think it is also possible with a reverse-operated (PIN) diode), there's probably a practical limitation on the substrate's doping concentration: the space charge region's thickness must be large enough to take over the lion's share of the voltage in order to save the MOS oxide from breakthrough, and so with the unfavorable dielectric constant ratio of 3 between Si and SiO2. I.e. with a MOSCAP, deep depletion can only be achieved on a lowly doped substrate; at a high doping concentration, the MOS oxide is likely to (destructively) break through before deep depletion can be achieved, I guess.

Pls. tell me, if you think I'm wrong again!

Click to expand...

I do not think that you can achieve "deep depletion" in a reverse biased p-n junction - the majority carriers will quickly establish a steady-state condition, with the response time equal to so-called dielectric relaxation time, which is less than a picosecond in reasonably doped semiconductors.

I think you are right that for a given applied voltage more voltage will drop on semiconductor in a deep depletion condition for a lightly doped substrate than for a heavily doped substrate, so the oxide breakdown will happen at a smaller applied voltage for MOS capacitor on a heavily doped substrate.

Max
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timof said:

I do not think that you can achieve "deep depletion" in a reverse biased p-n junction - the majority carriers will quickly establish a steady-state condition, with the response time equal to so-called dielectric relaxation time, which is less than a picosecond in reasonably doped semiconductors.

Click to expand...

Thanks again for your answer, Max!

I'm sure you're right with: the majority carriers will quickly establish a steady-state condition, with the response time equal to so-called dielectric relaxation time for a forward-biased p-n junction, but I'm not so sure if this is also valid for a reverse-biased p-n junction. I think majority carriers cannot cross the junction (due to the reverse voltage), hence the carrier generation is subject to thermal generation (or to an avalanche process at very high electrical field strength). If so, also a short dynamic "deep depletion" zone could be created. I'm not sure, however.

erikl said:

I'm sure you're right with: the majority carriers will quickly establish a steady-state condition, with the response time equal to so-called dielectric relaxation time for a forward-biased p-n junction, but I'm not so sure if this is also valid for a reverse-biased p-n junction. I think majority carriers cannot cross the junction (due to the reverse voltage), hence the carrier generation is subject to thermal generation (or to an avalanche process at very high electrical field strength). If so, also a short dynamic "deep depletion" zone could be created. I'm not sure, however.

Click to expand...

To the contrary - under forward bias of p-n junctions, electrons will diffuse into p-region (and become minority carriers there), and holes will diffuse into n-type region. To extract those carriers back (or having them recombine) takes time - that's why there is slow "reverse recovery" process that slows down the response of p-n junctions when they are switched from the ON to OFF state.

Under reverse bias, the carriers do not diffuse to the opposite type regions since there is a high potential barrier for them, and so they stay in their respective regions (electrons in n-type and holes in p-type) and remain majority carriers. Their speed of response to voltage changes is very fast, limited by a very short dielectric relaxation time. You can create a "deep depletion" condition by switching the voltage at a speed higher than the dielectric relaxation time.

Let's make an estimate: dielectric relaxation time is:

tau_d = eps * eps_0 * rho = 12 * 8.854e-14 F/cm * 0.5 Ohm*cm ~ 0.5 ps

where rho=0.5 Ohm*cm corresponds to silicon doped at 1e16 cm-3.

As you can see this is a very fast time scale...

Ok, Max, thank you for your explanation!

Can anyone answer me the following question about C-V data of TiO2/Si MOSCAP

Would you please explain why I am getting a pick on accumulation region as shown in the attached file where C-V data was obtained by sweeping voltage using keithley 4200 at 1MHz on my TiO2 ntype Si MOSCAP.

Looks more like a C-V curve for a pn-junction (left: forward, right: reverse biased) than for a MOSCAP.

The peak means min. depletion region width (in reverse biased state).