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CML/SCL layout advice

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oermens

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Hi, I want to do layout of some CML gates. Since there are no standard cells for this logic family (or are there?), what is the best way to do the layout? I figure symmetry is important, what else? Should transistors be drawn on a single active, or as they are arranged as in schematic (stacked diff pairs)? Would each diff pair need its own guard ring?

My design works in UHF range.

Thanks.
 

Depending on your technology, UHF could be considered high-speed (if you are working up to 3GHz). Symmetry is most important.
I would also try to minimize parasitic capacitance on the internal nodes. For 90nm and below, I would not put transistors in the same active but I do not think you need guard rings on each differential pair.
Moreover, I do not think that arranging transistors as in schematic gives you the best layout.
 
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    oermens

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    MSLayout

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Preparing layout

Hi,
I am writing a program in verilog/vHDL . After that how to create micrograph layout as shown below. Please give your advice.......

Sudan
 

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