generic vs constant in VHDL?

vhdl generic

Hi VHDL Guys,

What is the difference between generic and constant?

The only difference i know that the constant is declared only in architecure body not in the entity like the generic .

But they have the same application ( provide a static "constant" info to the model ) !!!

SphinX
Thanks in advance

generic vhdl

In good VHDL practices constants are declared in packages for global scope, generics cannot be declared inside a package.

Generics should not replace constants per say, i.e., you do not want to declare a vector of type std_logic_vector as generic. Many tools would let you use INTEGER generics only. Generics are good for simulation for example declaring something of type TIME. Generic is probably best used in conjunction of CONFIGURATION where you might want to describe several models of same device with different delays.

Constants can be deferred that is their value can be changed inside package body without compliing the whole design for last moment bindings. This cannot be done of generics.

Not all simulators handle generics.

Conclusion of the story: Generics are NOT a replacement of constants just a special type of constant and must be used with care.

vhdl constant

Oops

Didn't know there are so many shortcomings about generics.

Thanks delay for your information

vhdl generics

Hi,
As you have mentioned, Generic can be declared in entity. This is basically useful when you make multiple instances of a component. In case of multiple instances of a component you can have different value of generic for each instance. Lets take an example:
Say you want to instantiate a simple AND gate (just for example) and the component for this AND gate has a generic declared for its Propagation Delay. So you can have different value of propagation delay for each instance.
If the value of generic is not specified in instance then its default value is used which you can specify in the entity of this AND gate.
The value of generic specified during this instance is constant for that instance.
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Now lets say instead of generic you have declared a constant in entity of AND gate. In this case you cannot have different value of propagation delay for each instance.
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generic in vhdl

Generics serve to structurize the programming.
Constants in package looks like shared variables which exchange is prohibited.
If generics are substituted by constants
the project compiling is more simple,
but when project has a lot of instances, then the number of such constants is too high, and to follow them is a heavy task.

to know about constants :
https://vhdlguru.blogspot.com/2010/03/when-and-how-to-use-constant.html
to know about generics:
https://vhdlguru.blogspot.com/2010/03/generics-in-vhdl-construction-of.html

Hey guys I had a quick question relating to this. Can you use multiple generics in one entity?

Yes. You can have as many generics as you want, of whatever type you want.