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How to print an integer in VHDL

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raghava

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HI all,

How to print an integer in VHDL.

I am using following syntax.

report "Number of cycles taken = " & count_cycle;


Its giving error.

Can anybody correct it.

Regards

Added after 1 minutes:

Here count_cycle is variable.
 

I am afraid the message you type can be text only.
 

You're apparently refering to VHDL simulation. You should be able to find respective string conversion routines in textio package.

P.S.: I see, that report uses a generic STRING type argument, while textio.write uses the derived LINE type. It's not clear to me,
if they can be made compatible. Otherwise I would consult the simulator's user guide for suggestions.
 

HI Fvm,

Thanks for your answer.

In verilog we have $display("%d", 6);

In the same way how should I print in VHDL.
Here I have to print some variable which is stored with some integer value.


Regards
 

**broken link removed**
and **broken link removed**
--
Amr Ali
 

    R

    raghava

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HI Amar Ali and Frankliner,

Thanks for your answers. I am in desperate to know the syntax as I am in urgency.

Thanks for your answers.


Regards

Added after 3 hours 28 minutes:

HI all,

This syntax is working.

report "Number of cycles taken = " & integer'image(count_cycle);


even write() is also working.


Regards,
 

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