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finding crtitical path in the synthesized verilog code

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sudheerprasad

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hi,
i want to know the top ten(may vary) critical paths in my design,can be done while doin synthesis in design vision or should i take the synthesized verilog file and use any other synopsys tool
 

Re: finding critical paths in design vision

Yes, you can find your critical paths using Design Vision. Check your manual for report_timing. report_timing -max_path 10 will report the 10 worst paths per timing group.
 

you should synthesize the circuit and then find the longest path depending on the slack...met or neg..and the arrival times of diff ff...
 

you can use either design compiler (DC) or primetime (PT)

in your synthesis script, write a ddc format netlist (so that the constraints are embedded in the ddc file)

once you're done with synthesis and generated the ddc file, read it into either DC or PT. then do a report_timing -nworst 10 -max_paths 10. this will give the top 10 critical paths (with the largest negative slack, or with the smallest positive slack if it passes timing)
 

can we findout the paths having the max positive slack i.e least delay
 

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