subagha
Newbie level 3
Hi,
I have a small design in VHDL with black box which i am trying to synthesize
using Xilinx ISE 11.2.
I get an error when running the command ngdbuild.
ERROR:NgdBuild:604 - logical block 'inst' with type 'my_block' could not be
resolved. A pin name misspelling can cause this, a missing edif or ngc file,
or the misspelling of a type name. Symbol 'my_block' is not supported in
target 'virtex5'.
The design has two files
my_block.vhd ---
library ieee;
use ieee.std_logic_1164.all;
entity my_block is
port(I1, I2 : in std_logic;
O : out std_logic);
end my_block;
architecture tmp of my_block is
begin
end tmp;
black_box_1.vhd ---
library ieee;
use ieee.std_logic_1164.all;
entity black_box_1 is
port(DI_1, DI_2 : in std_logic;
DOUT : out std_logic);
end black_box_1;
architecture archi of black_box_1 is
component my_block
port (I1 : in std_logic;
I2 : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE: string;
attribute BOX_TYPE of my_block: component is "BLACK_BOX";
begin
inst: my_block port map (I1=>DI_1,I2=>DI_2,O=>DOUT);
end archi;
I am using the commandline to run my commands and not the GUI.
command which generated error:
ngdbuild -intstyle xflow -sd . -dd _ngo -nt timestamp -p xc5vtx240t-2ff1759 black_box_1.ngc black_box_1.ngd
I am a newbie to XST. So your help is most appreciated. Please explain
all the steps i need to do as i am a newbie to XST. I normally use
command line to run the tools so please send across a solution for
command line.
Thanking you in advance
regards,
suba
I have a small design in VHDL with black box which i am trying to synthesize
using Xilinx ISE 11.2.
I get an error when running the command ngdbuild.
ERROR:NgdBuild:604 - logical block 'inst' with type 'my_block' could not be
resolved. A pin name misspelling can cause this, a missing edif or ngc file,
or the misspelling of a type name. Symbol 'my_block' is not supported in
target 'virtex5'.
The design has two files
my_block.vhd ---
library ieee;
use ieee.std_logic_1164.all;
entity my_block is
port(I1, I2 : in std_logic;
O : out std_logic);
end my_block;
architecture tmp of my_block is
begin
end tmp;
black_box_1.vhd ---
library ieee;
use ieee.std_logic_1164.all;
entity black_box_1 is
port(DI_1, DI_2 : in std_logic;
DOUT : out std_logic);
end black_box_1;
architecture archi of black_box_1 is
component my_block
port (I1 : in std_logic;
I2 : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE: string;
attribute BOX_TYPE of my_block: component is "BLACK_BOX";
begin
inst: my_block port map (I1=>DI_1,I2=>DI_2,O=>DOUT);
end archi;
I am using the commandline to run my commands and not the GUI.
command which generated error:
ngdbuild -intstyle xflow -sd . -dd _ngo -nt timestamp -p xc5vtx240t-2ff1759 black_box_1.ngc black_box_1.ngd
I am a newbie to XST. So your help is most appreciated. Please explain
all the steps i need to do as i am a newbie to XST. I normally use
command line to run the tools so please send across a solution for
command line.
Thanking you in advance
regards,
suba