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Problem with Black Box in VHDL in ISE 11.2 :: ERROR:NgdBuild

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Newbie level 3
Oct 13, 2009
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I have a small design in VHDL with black box which i am trying to synthesize
using Xilinx ISE 11.2.

I get an error when running the command ngdbuild.
ERROR:NgdBuild:604 - logical block 'inst' with type 'my_block' could not be
resolved. A pin name misspelling can cause this, a missing edif or ngc file,
or the misspelling of a type name. Symbol 'my_block' is not supported in
target 'virtex5'.

The design has two files

my_block.vhd ---
library ieee;
use ieee.std_logic_1164.all;

entity my_block is
port(I1, I2 : in std_logic;
O : out std_logic);
end my_block;

architecture tmp of my_block is


end tmp;

black_box_1.vhd ---

library ieee;
use ieee.std_logic_1164.all;

entity black_box_1 is
port(DI_1, DI_2 : in std_logic;
DOUT : out std_logic);
end black_box_1;

architecture archi of black_box_1 is

component my_block
port (I1 : in std_logic;
I2 : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE: string;
attribute BOX_TYPE of my_block: component is "BLACK_BOX";


inst: my_block port map (I1=>DI_1,I2=>DI_2,O=>DOUT);

end archi;

I am using the commandline to run my commands and not the GUI.

command which generated error:
ngdbuild -intstyle xflow -sd . -dd _ngo -nt timestamp -p xc5vtx240t-2ff1759 black_box_1.ngc black_box_1.ngd

I am a newbie to XST. So your help is most appreciated. Please explain
all the steps i need to do as i am a newbie to XST. I normally use
command line to run the tools so please send across a solution for
command line.

Thanking you in advance


XST does not accept multiple names declared on the same line. Split the name declarations of t he inputs on the entity and the problem will be solved.

Re: Problem with Black Box in VHDL in ISE 11.2 :: ERROR:NgdB

Hi farhada,
Thanks for the reply.

i tried by splitting the name declarations of the inputs for both of my blocks and it did not solve my problem. Still i get the same error.


Added after 2 hours 59 minutes:


I even tried by synthesizing the my_block.vhd and placing the my_block.ngc in the current directory where ngdbuild is run but the error is not gone.

I have checked with the previous versions old ISE till 9.2i, but i still get the error.

I even use the switches '-iob false' and 'iobuf no' while synthesizing my_block.vhd.

Still the problem is not solved.

I used other synthesis tools like synplicity and Quartus but could not face any problems there with black boxing as its pretty simple in the tools



Re: Problem with Black Box in VHDL in ISE 11.2 :: ERROR:NgdB

Ok, compiled the code in ISE 10.1.03 and it works in synthesis, the fails in place and route which is correct.

Synthesis creates a black box (automatically since the architecture is empty) but in place and route, the empty architecture with no logic in it, don't work. If you put some logic in the architecture of the my_block and then create the ngc file in the same directory were ISE is compiling and it works.

Once again, your problem is not synthesis, but place and rout.

Best regards,
/Farhad Abdolian


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Re: Problem with Black Box in VHDL in ISE 11.2 :: ERROR:NgdB

Thanks for the solutions.


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