ESD structure design for particular specification

ESD design

I'm going to design an output driver using a 0.35um tripple-well bicmos process. The supply voltage of this output driver is Vdd=3.3V, and Vss=0V.
In really application, the Output pin could be accidentally connected to 16V (>3.3V) or -16V external unregulated battery. Customer's SPEC is that, not matter which of these two wrong connections happens, the output current Iout shoud be limited to less than 1mA. That means in ESD circuit, there shouldn't be any diode between Vdd and Out or Out and Vss. What kind of ESD structure could meet this SPEC?

The following is my understanding, Vt1 (first triggering voltage)should be great than 16V, but less than breakdown voltage of devices connected to Output pin, Vh (snap-back hold voltage) should be less than 3.3V. Also, in ESD structure, there is no direct path or at least some kind of resistance between Out and Vdd when Out=16V and Vdd=3.3V. The same for Vss, there is no direct path between Vss and Out when Vss=0V and Out=-16V. Just don't what kind ESD structure can achieve this target.

ESD design

MILSCR (Mirrored Lateral SCR) device, having symmetrical +/- behaviour in breakdown I think. But I can't to understand how to protect 0.35um gates (70nm oxide with BVox ~ 15...20V ?). Do you have double oxide (e.g. 3.3V&16V ) option? In that case task can be simplified.

Re: ESD design

Hi Tia_design

You will need to work with local protection clamps between Pad and Vss and between Vdd and pad or like Mikersia explains a bi-directional clamp between pad and vss or bidirectional between pad and Vdd.

However, just like Mikersia I fear that a standard digital CMOS output scheme for 3.3V based on 0.35um 3.3V transistors will not survive ESD when the trigger and clamping voltage is above 16V. If you can use 16V transistors for this (output driver) purpose then you may get it to work.

Note that I do not believe that it is tolerated to have a MILSCR protection clamp for this application as the holding voltage is way below the 16V. This is also a problem in the description from tia_design ("Vh should be less than 3.3V"). If the holding voltage is indeed below 16V than you will create a sort of latch-up leading to an empty battery and possibly smoke in the circuit!

ES

ESD design

Hi ESDSolutions

HHI + MILSCR (Vt1~20V) + triple (quadrupole?) PMOS/NMOS cascodes?

Re: ESD design

Hi, Mikersia and ESDSolutions

Yes you are right. In this process I have high voltage devices with thick gate oxide. The output device directly connected to the output pin is HV NMOS and HV PMOS. The can sustain 18V.

Re: ESD design

Hi Tia_design

OK: 18V tolerant HVNMOS/HVPMOS solves the problem. Now you just need to define the ESD clamp to protect the HVNMOS.

Be sure to decouple the Nwell (PMOS driver) from the 3.3V Vdd line to disable the diode up intrinsic in the PMOS. Similarly you will need to disable the diode inside the HVNMOS by isolating its bulk.

Mikersia: What do you mean by 'HHI'?

ES

Re: ESD design

ESDSolutions said:

Hi Tia_design

OK: 18V tolerant HVNMOS/HVPMOS solves the problem. Now you just need to define the ESD clamp to protect the HVNMOS.

Be sure to decouple the Nwell (PMOS driver) from the 3.3V Vdd line to disable the diode up intrinsic in the PMOS. Similarly you will need to disable the diode inside the HVNMOS by isolating its bulk.

Mikersia: What do you mean by 'HHI'?

ES

Click to expand...

Hi, ESDSolutions,
Thanks a lot for your quick reply. I'm not in ESD design field. But because of limited resource in my current company. I was asked to try this design. So, some points of ESD design is straight forward for you, but hard for me to understand:
"OK: 18V tolerant HVNMOS/HVPMOS solves the problem. " Why you say HVNMOS/HVPMOS solves the problem. Does that mean HVNMOS and HVPMOS self-protected from ESD stress?
"Now you just need to define the ESD clamp to protect the HVNMOS. " Why not to define the ESD calmp to protecte the HVNMOS, not HVPMOS? Thanks again

Re: ESD design

Hi Tia_design

1. "HVNMOS/HVPMOS solves the problem": I meant that this solves the problem for the possible wrong connections: the circuit will not get damaged from the +/-16V connections: the drivers should be able to reliably sustain these applied voltages. But this does not solve the ESD problem yet of course - certainly the HVNMOS cannot be made self-protective.

2. For ESD: In my experience HVPMOS could be made self-protective by using the right device size. HVNMOS will need a parallel ESD protection element. Since this protection must be over voltage tolerant AND under voltage tolerant it is not an easy one - good luck!

3. You should start by finding out the so-called ESD design window maximum voltage: at which (transient) voltage (>16V) will the HVNMOS fail... knowing that its bulk is not connected to the source and for random gate bias.

ESD design

Hi ESDSolutions

HHI - High Hold Current, e.g. > 100mA

Tia_design: what time you have to increase background in ESD protection design? I avoide that it is nearly impossible to get necessary knowledge (especially in HV protection) during a weeks...monthes. If project don't suppose mass production, it is better to omit thus issue.

Re: ESD design

Hi Mikersia

HHI - High Holding Current. There are indeed different techniques to increase the holding current of the SCR. However, many of these techniques (e.g. breaking up the anode/cathode to insert well taps) are covered by patents.

This means that you will need to obtain a license for technology once you move to commercial production of the parts

ES