Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Question about signal mux

Status
Not open for further replies.
E

EDA_hg81

Advanced Member level 2
Joined
Nov 25, 2005
Messages
507
Helped
2
Reputation
4
Reaction score
2
Trophy points
1,298
Activity points
4,808
I have two circuit expression of signal mux : the first one is a combination circuit and the second one is a sequential circuit.

Which expression is more effective?

Can the sequential circuit miss the transition period of signals?

Code: 
invertvsync     <= not(sysvsync) when inversevs = '1' else sysvsync;

Code: 
process ( refclk ) 
	begin
		if (rising_edge(refclk)) then
                            if (inversevs = ‘1’ ) then
                               invertvsync     <= not(sysvsync);
                            else
                                invertvsync    <= sysvsync;
                            end if;
        end if;   
end process;

Thanks.
 

Both the multiplexers you describe are identical, except that the 2nd one is followed by a flip-flop (the 'data' input of the flip-flop has the same multiplexer as the 1st).

So, from a multiplexer point of view they are the same (both have the same 'effectiveness'). Clocking it in makes the signal stable from clock-to-clock period. The clocked process will only 'remember' the state at the rising edge of the clock. All changes that occur before that will not appear at the output (nor will changes until the next clock).
 

    E

    EDA_hg81

    Points: 2
    Helpful Answer Positive Rating
Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top