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How to change this coding to 8 8 bit register?

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tss

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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

ENTITY alu8bit is
port(A, B : in std_logic_vector(7 downto 0);
op : in std_logic_vector(2 downto 0);
zero : out std_logic;
C: out std_logic_vector(7 downto 0));
END alu8bit;

architecture behavioral of alu8bit is
begin
process(op)
variable temp: std_logic_vector(7 downto 0);
begin
case op is
when "000" =>
temp := a and b;
when "100" =>
temp := a and b;
when "001" =>
temp := a or b;
when "101" =>
temp := a or b;
when "010" =>
temp := a + b;
when "110" =>
temp := a - b;
when "111" =>
if a < b then
temp := "11111111";
else
temp := "00000000";
end if;
when others =>
temp := a - b;
end case;
if temp="00000000" then
zero <= '1';
else
zero <= '0';
end if;
c <= temp;
end process;
end behavioral;



anyone know how to change the coding above to 8 8 bit register ?
 

error (10309): vhdl interface declaration error

What you need is a port array. Something like:
Code: 
  type port_array is array(7 downto 0) of std_logic_vector(7 downto 0);
  signal my_signal: port_array;

You might have to declare your user-defined data type in a package, if you want to use it in the entity.
It would them be something like this (unchecked):

Code: 
-- package
...
package user_defined_types is
  type port_array is array(7 downto 0) of std_logic_vector(7 downto 0);
end user_defined_type


-- application
...
use work.user_defined_types.all;   -- your package

entity your_app
  port (
    input: in port_array;
    ...
  );
end app;
  ....
 

error (10309): vhdl interface declaration error

can you explain with more detail ?
i want the design contain 8 8-bit registers which can be loaded from an external input and loaded back into one of the eight internal registers, or read externally.
 

check huigh bit on std_logic_vector

Here is a 'component' which has 8*8 registers and can be read/written to/from.
Is is not clocked and as such is not typically used.


Code: 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

ENTITY alu8bit is
  port(
    indexin : in natural range 0 to 7;
    datain  : in  std_logic_vector(7 downto 0);
    indexout: in natural range 0 to 7;
    dataout : out std_logic_vector(7 downto 0)
  );
END alu8bit;

architecture behavioral of alu8bit is
  type   portarray is array(7 downto 0) of std_logic_vector(7 downto 0);
  signal internalregisters: portarray;
  
begin
  internalregisters(indexin) <= datain;
  dataout <= internalregisters(indexout);
end behavioral;

Typically you use a clocked design, were the data is latched at the rising edge of the clock.

Code: 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

ENTITY alu8bit is
  port(
    clk     : in std_logic;
    indexin : in natural range 0 to 7;
    datain  : in  std_logic_vector(7 downto 0);
    indexout: in natural range 0 to 7;
    dataout : out std_logic_vector(7 downto 0)
  );
END alu8bit;

architecture behavioral of alu8bit is
  type   portarray is array(7 downto 0) of std_logic_vector(7 downto 0);
  signal internalregisters: portarray;
  
begin
  process(clk)
  begin
    if rising_edge(clk) then
      internalregisters(indexin) <= datain;
    end if;
  end process;
  
  process(clk)
  begin
    if rising_edge(clk) then
      dataout <= internalregisters(indexout);
    end if;
  end process;
  
end behavioral;

And there are variations on this, like using read/write inputs:
Code: 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

ENTITY alu8bit is
  port(
    clk     : in std_logic;
    write   : in std_logic;
    indexin : in natural range 0 to 7;
    datain  : in  std_logic_vector(7 downto 0);
    read    : in std_logic;
    indexout: in natural range 0 to 7;
    dataout : out std_logic_vector(7 downto 0)
  );
END alu8bit;

architecture behavioral of alu8bit is
  type   portarray is array(7 downto 0) of std_logic_vector(7 downto 0);
  signal internalregisters: portarray;
  
begin
  process(clk)
  begin
    if rising_edge(clk) then
      if write = '1' then
        internalregisters(indexin) <= datain;
      end if;  
    end if;
  end process;
  
  process(clk)
  begin
    if rising_edge(clk) then
      if read = '1' then
        dataout <= internalregisters(indexout);
      end if;  
    end if;
  end process;
  
end behavioral;

And we could combine read/write, make the data bidirectional etc, etc.
 

    T

    tss

    Points: 2
    Helpful Answer Positive Rating
mar mar lwin 8 8 bit register

thanks Marcel Majoor. i will come back again if any doubt.
 

8 8bit register

i do not understand this line >>>>>>>>> indexin : in natural range 0 to 7;

can someone tell me ?
 

vhdl error (10309):

hai..you good student ah

Added after 46 seconds:

who are you? please come to my office!!
 

8 8 bit register

.. in natural range 0 to 7;

This means we define a 'natural', which can have a range from '0' to '7'.
A 'natural' is a user-defined integer type, which has a default range from 0 to +2147483647.
If we did not include the range (range 0 to 7), then we would have the default range of the 'natural'.

Basically we could also have 'indexin' and 'indexout' defined as a std_logic_vector(2 downto 0), which happens also to have 8 possible values, but using a natural (and defining its range) does it too.
We leave it up to the compiler to 'allocate' the correct number of bits for it.
Sometimes it is just more convenient to use an integer/natural, instead of a std_logic_vector. Some operations, like using it as the index for an array, can be done without additional conversion/'typecasting'.
 

vhdl 8 8 bits register

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

ENTITY alu8bit is
port(
a : in natural range 0 to 7;
b: in std_logic_vector(7 downto 0);
c: in natural range 0 to 7;
op : out std_logic_vector(2 downto 0)
);
END alu8bit;

architecture behavioral of alu8bit is
begin
process(op)
variable temp: std_logic_vector(7 downto 0);
begin
case op is
when "000" =>
temp := a and b;
when "100" =>
temp := a and b;
when "001" =>
temp := a or b;
when "101" =>
temp := a or b;
when "010" =>
temp := a + b;
when "110" =>
temp := a - b;
when "111" =>
if a < b then
temp := "11111111";
else
temp := "00000000";
end if;
when others =>
temp := a - b;
end case;
if temp="00000000" then
zero <= '1';
else
zero <= '0';
end if;
c <= temp;
end process;


end behavioral;

i try this but i got the following erros.
Info: Running Quartus II Analysis & Synthesis
Info: Version 9.0 Build 184 04/29/2009 Service Pack 1 SJ Web Edition
Info: Processing started: Sat Jul 18 00:55:36 2009
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off alu8bit -c alu8bit
Info: Found 2 design units, including 1 entities, in source file alu8bit.vhd
Info: Found design unit 1: alu8bit-behavioral
Info: Found entity 1: alu8bit
Error (10309): VHDL Interface Declaration error in alu8bit.vhd(20): interface object "op" of mode out cannot be read. Change object mode to buffer.
Error (10309): VHDL Interface Declaration error in alu8bit.vhd(17): interface object "op" of mode out cannot be read. Change object mode to buffer.
Error: Quartus II Analysis & Synthesis was unsuccessful. 2 errors, 0 warnings
Error: Peak virtual memory: 215 megabytes
Error: Processing ended: Sat Jul 18 00:55:38 2009
Error: Elapsed time: 00:00:02
Error: Total CPU time (on all processors): 00:00:01
Error: Quartus II Full Compilation was unsuccessful. 4 errors, 0 warnings
 

design an 8 bit register

if write = '1' then ....
if read = '1' then.....

what the function for two line above ?
sorry miss, i am learning from here also. please don't call me to your office. :cry:
 

Re: 8 8 bit resgister

Error (10309): VHDL Interface Declaration error in alu8bit.vhd(20): interface object "op" of mode out cannot be read. Change object mode to buffer.

The 'op' is defined in the entity as an output, so it can be an 'input' for the process.
Your 'op' most likely needs to be an 'in' instead of an 'out'. And your c port probably need to be 'out' instead of 'in'.

Here is your code but slightly modified to be compilable:
Modified parts are:
port a/b: -> std_logic_vector(7 downto 0)
port c: out
op: in
signal zero added

Code: 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

ENTITY alu8bit is
  port(
    a : in  std_logic_vector(7 downto 0);
    b : in  std_logic_vector(7 downto 0);
    c : out std_logic_vector(7 downto 0);
    op: in  std_logic_vector(2 downto 0)
  );
END alu8bit;

architecture behavioral of alu8bit is
  signal zero: std_logic;
  
begin

  process(op)
    variable temp: std_logic_vector(7 downto 0);
  begin
    case op is
      when "000"  => temp := a and b;
      when "100"  => temp := a and b;
      when "001"  => temp := a or b;
      when "101"  => temp := a or b;
      when "010"  => temp := a + b;
      when "110"  => temp := a - b;
      when "111"  => if a < b then
                       temp := "11111111";
                     else
                       temp := "00000000";
                     end if;
      when others => temp := a - b;
    end case;
    if temp="00000000" then
      zero <= '1';
    else
      zero <= '0';
    end if;
    c <= temp;
  end process;


end behavioral;

Added after 7 minutes:

With the 'read' and 'write' signals one indicates that either a read (read='1') or a write (write='1') is to be performed.

Code: 
1:  process(clk)
    begin
2:    if rising_edge(clk) then
3:      if write = '1' then
4:        internalregisters(indexin) <= datain;
        end if; 
     end if;
    end process;

This code says:
1: when the signal 'clk' changes then the process is activated
2: if 'clk' is a rising edge then ...
3: if the 'write' signal is asserted then
4: register 'datain' to 'internalregisters' (which of the 8 is set by 'indexin')
 

Re: 8 8 bit resgister

hai thanks for the coding.i have tested and its working.does this coding contain 8*8-bit register_ALU?
 

Re: 8 8 bit resgister

i got it, thanks Marcel Majoor.
here got one and last thing i don't understand.
internalregisters(indexin) <= datain;
datain store in indexin or internalregisters ?

if i am not wrong 'internalregisters' is an array which contain 8*8 bit register right ?
 

Re: 8 8 bit resgister

tss said:
i got it, thanks Marcel Majoor.
here got one and last thing i don't understand.
internalregisters(indexin) <= datain;
datain store in indexin or internalregisters ?
Click to expand...

hey who r u ?whic code u using now?
 

Re: 8 8 bit resgister

mar mar lwin said:
tss said:
i got it, thanks Marcel Majoor.
here got one and last thing i don't understand.
internalregisters(indexin) <= datain;
datain store in indexin or internalregisters ?
Click to expand...

hey who r u ?whic code u using now?
Click to expand...

i am trying to do 8*8 bit register now.
there are a lot of error in my code, so i need to modify some parts and recompile again. miss, i am not copying so don't be so angry. :D
 

Re: 8 8 bit resgister

HOW TO MODIFY THIS CODE TO MAKE IT 8*8 REGISTER?? YOU HV ANY IDEA?
 

Re: 8 8 bit resgister

Code: 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

ENTITY alu8bit is
port(
    indexin : in  std_logic_vector(7 downto 0);
    datain  : in  std_logic_vector(7 downto 0);
    A : in std_logic_vector(7 downto 0); 
    B : in std_logic_vector(7 downto 0);
    op : in std_logic_vector(2 downto 0);
    zero : out std_logic;
    C: out std_logic_vector(7 downto 0)
	);
END alu8bit;

architecture behavioral of alu8bit is
begin
process(clk)
type portarray is array(7 downto 0) of std_logic_vector(7 downto 0); --array is to make 1*8 bit register to 8*8 bit registers
signal internalregisters: portarray;   -- 8*8 bit registers
	begin
		if rising_edge(clk) then
		internalregisters(indexin) <= datain; --'datain' store in 8*8 bit registers 
		a <= internalregisters(indexin) ;  --'a' get the data from 8*8 bit registers 
		b <= internalregisters(indexin) ; -- 'b' get the data from 8*8 bit registers
		end if;
	end process;
process(op)
variable temp: std_logic_vector(7 downto 0);
	begin
		case op is
			when "000" =>
			temp := a and b;  
			when "100" =>
			temp := a and b;
			when "001" =>
			temp := a or b;
			when "101" =>
			temp := a or b;
			when "010" =>
			temp := a + b;
			when "110" =>
			temp := a - b;
			when "111" =>
			if a < b then
			temp := "11111111";
			else
			temp := "00000000";
			end if;
			when others =>
			temp := a - b;
		end case;
	if temp="00000000" then
	zero <= '1';
	else
	zero <= '0';
	end if;
	c <= temp;
	end process;
	
end behavioral;
\]
i tried to compile the coding above but 3 errors are appeared. There some definition beside the coding, please correct it if i am wrong. thank you
 

Re: 8 8 bit resgister

1. Added clk in the entity part
2. 'Type' and 'signal' belong under the 'architecture' part of the design
3. IndexIn is too 'wide'. It allows an index ranging from 0..255 (8 bits), and the portarray only is 8 deep (3 bits).
I have made the portarray 'variable' so it uses the size of the IndexIn signal.
4. Added 'conv_integer' so the different 'types' match (std_logic_vector() -> natural)
5. Commented out A/B in the process. They are inputs in the entity, so they can never be written to. Only an 'out' or 'inout' can be written to (this applies to the entity signals only). Local signals (under architecture) are always 'inout', but as you know they can only be written to in single process.

entity part: the 'outside' world
architecture: the 'local' signals/definition

Here is a 'compilable' version.
Please note that using 'correct' indentations make the code more readable, and therefore easier to understand.

Code: 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

ENTITY alu8bit is
  port(
    clk     : in  std_logic;
    indexin : in  std_logic_vector(2 downto 0);
    datain  : in  std_logic_vector(7 downto 0);
    A       : in  std_logic_vector(7 downto 0);
    B       : in  std_logic_vector(7 downto 0);
    op      : in  std_logic_vector(2 downto 0);
    zero    : out std_logic;
    C       : out std_logic_vector(7 downto 0)
  );
END alu8bit;

architecture behavioral of alu8bit is
  type   portarray is array(indexin'HIGH downto indexin'LOW) of std_logic_vector(7 downto 0); -- array of byte based registers
  signal internalregisters: portarray;                                                        -- byte registers
  
begin
  process(clk)
  begin
    if rising_edge(clk) then
      internalregisters(conv_integer(indexin)) <= datain;     -- 'datain' store in array of byte registers
-- impossible -> 'A' is defined as 'in' in entity!      a <= internalregisters(conv_integer(indexin));          -- 'a' get the data from array of byte registers
-- impossible -> 'B' is defined as 'in' in entity!      b <= internalregisters(conv_integer(indexin));          -- 'b' get the data from array of byte registers
    end if;
  end process;
  
  process(op)
    variable temp: std_logic_vector(7 downto 0);
  begin
    case op is
      when "000"  => temp := a and b; 
      when "100"  => temp := a and b;
      when "001"  => temp := a or b;
      when "101"  => temp := a or b;
      when "010"  => temp := a + b;
      when "110"  => temp := a - b;
      when "111"  => if a < b then
                       temp := "11111111";
                     else
                       temp := "00000000";
                     end if;
      when others => temp := a - b;
    end case;
    if temp="00000000" then
      zero <= '1';
    else
      zero <= '0';
    end if;
    c <= temp;
  end process;
   
end behavioral;
 

    T

    tss

    Points: 2
    Helpful Answer Positive Rating
Re: 8 8 bit resgister

Code: 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

ENTITY alu8bit is
  port(
    clk     : in  std_logic;
    indexin : in  std_logic_vector(2 downto 0);
    datain  : in  std_logic_vector(7 downto 0);
    A       : out  std_logic_vector(7 downto 0);
    B       : out  std_logic_vector(7 downto 0);
    op      : in  std_logic_vector(2 downto 0);
    zero    : out std_logic;
    C       : out std_logic_vector(7 downto 0)
  );
END alu8bit;

architecture behavioral of alu8bit is
  type   portarray is array(indexin'HIGH downto indexin'LOW) of std_logic_vector(7 downto 0); -- array of byte based registers
  signal internalregisters: portarray;                                                        -- byte registers
 
begin
  process(clk)
  begin
    if rising_edge(clk) then
      internalregisters(conv_integer(indexin)) <= datain;     -- 'datain' store in array of byte registers
-- impossible -> 'A' is defined as 'in' in entity!      
a <= internalregisters(conv_integer(indexin));          -- 'a' get the data from array of byte registers
-- impossible -> 'B' is defined as 'in' in entity!    
 b <= internalregisters(conv_integer(indexin));          -- 'b' get the data from array of byte registers
    end if;
  end process;
 
  process(op)
    variable temp: std_logic_vector(7 downto 0);
  begin
    case op is
      when "000"  => temp := a and b;
      when "100"  => temp := a and b;
      when "001"  => temp := a or b;
      when "101"  => temp := a or b;
      when "010"  => temp := a + b;
      when "110"  => temp := a - b;
      when "111"  => if a < b then
                       temp := "11111111";
                     else
                       temp := "00000000";
                     end if;
      when others => temp := a - b;
    end case;
    if temp="00000000" then
      zero <= '1';
    else
      zero <= '0';
    end if;
    c <= temp;
  end process;
   
end behavioral;

i try this but it shown the error as below :
Error (10309): VHDL Interface Declaration error in alu8bit.vhd(39): interface object "A" of mode out cannot be read. Change object mode to buffer.
Error (10309): VHDL Interface Declaration error in alu8bit.vhd(39): interface object "B" of mode out cannot be read. Change object mode to buffer.
Error: Quartus II Analysis & Synthesis was unsuccessful. 2 errors, 0 warnings
Error: Peak virtual memory: 183 megabytes
Error: Processing ended: Sun Jul 19 21:50:21 2009
Error: Elapsed time: 00:00:02
Error: Total CPU time (on all processors): 00:00:02
Error: Quartus II Full Compilation was unsuccessful. 4 errors, 0 warnings

Added after 31 minutes:

internalregisters(conv_integer(indexin)) <<<< this line indicated 8*8 bits registers isn't it ?

type portarray is array(indexin'HIGH downto indexin'LOW) of std_logic_vector(7 downto 0); <<<< sorry, actually i don't really undersand this line..

can you show me which part of the previous coding was making 8*8 bits register ?

i want a and b get the data from 8*8 bit registers and then operate in process(op).
 

Re: 8 8 bit resgister

+++++++++++++++++
internalregisters(conv_integer(indexin)) <<<< this line indicated 8*8 bits registers isn't it ?


This is equivalent with 'internalregisters(indexin)'.
When using
Code: 
  type   portarray is array(2 downto 0) of std_logic_vector(7 downto 0);
  signal internalregisters: portarray;

it means we have the following signals:
Code: 
  internalregisters(0) -> which is a std_logic_vector(7 downto 0) == 8 bit register
  internalregisters(1) -> which is a std_logic_vector(7 downto 0) == 8 bit register
  internalregisters(2) -> which is a std_logic_vector(7 downto 0) == 8 bit register
If 'indexin' is 2 then with 'internalregisters(indexin)' we would be adressing internalregisters(2) .

To make it more clear you can 'expand' the 'type' line into the 'signal' line. Just replace 'portarray' on the signal line with it's definition, like so:
Code: 
  signal internalregisters: array(2 downto 0) of std_logic_vector(7 downto 0);;

+++++++++++++++++
type portarray is array(indexin'HIGH downto indexin'LOW) of std_logic_vector(7 downto 0); <<<< sorry, actually i don't really undersand this line..

You probably don't understand indexin'HIGH and indexin'LOW.
indexin'HIGH --> means the high range of 'indexin' -> in this case '2'
indexin'LOW --> means the low range of 'indexin' -> in this case '0'

Using this 'high and 'low (these are so called data attributes) we don't have to change code when the range of 'indexin' changes. Other attributes are:
'left -> leftmost array index
'right -> rightmost array index
'length -> vector size
'range -> vector range
'reverse_range -> reversed vector range
Suppose we have a
signal Check: std_logic_vector(3 to 6);
then
Check'high --> 6
Check'low --> 3
Check'left --> 3
Check'right -> 6
Check'length -> 4
Check'range -> (3 to 6)
Check'reverse_range -> (6 downto 3)



+++++++++++++++++
can you show me which part of the previous coding was making 8*8 bits register ?

i want a and b get the data from 8*8 bit registers and then operate in process(op).

Whenever you are addressing 'internalregisters()' then you are actually addressing the whole 8 bit register, since 'internalregisters()' is of type 'std_logic_vector(7 downto 0)'.
So, with
Code: 
  signal a, b, c: std_logic_vector(7 downto );
then
Code: 
  c <= a or b;
is essentially:
Code: 
  c(7 downto 0) <= a(7 downto 0) or b(7downto 0);


Note that with 'internalregisters(0)' we are actually saying 'internalregisters(0)(7 downto 0)' --> all 8 bits of the 8-bit register internalregister '0'.
 

    T

    tss

    Points: 2
    Helpful Answer Positive Rating
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