Calibre LVS problem in AMI 0.5um

bad component subtype

Hi every body,
I am trying to make my LVS working with calibre,
I couldnt find the file LVS.rul, I have lvs.ctrl and lvs.include, so I used the calibreEXTc5.rul file since LVS does extracting and I was hoping that calibre make the matching with the schematic netlist.
I beleive this is the wrong part, cause I didnt give any thing to calibre to make comparison.

the result I got is, the process works perfectly but no device was recognized, I mean no transistors ...

I tried the same thing, with a very simple layout, just a layout of a single transistor !!! and I got the same error, "bad component subtype"

I am wondering what did wrong ?

is there any one who used the 0.5um ami process ? if yes how did you do your lvs and what is the file rule you used.

thanx

calibre lvs bad component subtype

May be netlist subtype and lvs.include subtype of transistors are different?

lvs bad component subtype

hi, thank you for your answer.
what do you mean by netlist subtype and lvs.include subtype of transistors,

I didn't even use the lvs.include, I get error when I use it.

0.5um

In one of your calibre lvs files the devices of transistors and other elements of topology must be defined. For example so:

DEVICE MN(nto) Nchannel_thickox Poly_nodev(G) Nsd_all(S) Nsd_all(D) Pwell(B) <Active>
...

here "nto" is subtype of transistor. He must be the same as in netlist:

M35 Dm35 ref1 net0207 GRND nto w=1.1u l=1.7u

otherwise there will be a error report about distinction of subtype transistor.

component subtype

oooh thank you man !!!
this is the origin of the problem the bad subtype was exactely this.
in my source netlist I had transistor MN(NM) and in the layout MN(N), the subtype NM doesn't exist in my models and I don't know why it's extracted that way

so I changed it in the netlist source generated by calibre juste to see what happens, I made it the same as the layout and it works

now that I know where is the problem, I have to understand why the tool generate a wrong subtype transistor, taking into account that when I do my simulation with analog environment the transistor subtype is right and not (nm)