Need Help in vhdl Code for input+100 points for working code

khamitkar.ravikant said:

hi all
i am designing the code for AES system
as system works on 128bit data and 128 bit of key
i am ready with all module which work on data path of 128 bits
but i want a input to external entity in the form of 32bit
as input text as 32 bit data input simillerly key input is 32 bit and output
is 32 bit.
so all this should come inside with clock cycles and output should work after internal logic
is over and output with clock synchronus way.
so i need help in this regard if some buddy help me please
i will be greatful to him/her for kind help.

example code

as
entity core is
port ( clk : in std_logic;
textIn : in std_logic_vector (31 downto 0);
keyIn : in std_logic_vector(31 downto 0);
textOut : out std_logic_vector(31 downto 0)
);
architecture rtl of core is
signal --------------------
begin
process(clk)
variable ----------for registers--------
begin
if(clk='1' and clk'event ) then
variable as per case statement
end process;
end rtl;

please do somebuddy help me.
as my logic not working here
as i tried alot.
thanks alot

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