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Opamp circuit question

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EDA_hg81

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I am using TINA to simulate my cascaded opamp circuit implemented by LT1807.

My question is when I did the transient analysis on 100KHZ and 3MHZ input siganls, why the outputs are so different?

the gain for each stage is only 2.

Under 100khz input signals the output is right.

But the results for 3MHZ input signals are totally wrong; the outputs look like have been low passed.

The GBW of LT1807 is 325MHZ with frequency 6MHZ.

Please help, thanks.
 

Not decipherable component values, unfortunately. At least, the circuit has low pass functions, however.
 

The schematic was saved as a fuzzy JPG file type instead of as a very clear GIF or PNG file type.
The parts are spread out over my entire neighbourhood so they are very tiny.

Why do people post schematics that cannot be seen??
 

Yes, only the last opamp is the second order low pass filter.

Second opamp is the buffer.

Third opamp is for inverting the polarity of signals.

But the output signals from first opamp become small when frequency higher.

Why?


https://obrazki.elektroda.pl/3_1221367051.jpg
 

Your schematic was saved as a fuzzy JPG file type instead of as a very clear GIF or PNG file type.

The parts on your schematic are spread out over my entire neighbourhoiod so they are tiny and cannot be seen clearly.

This is a copy of part of your schematic. I increased its size and contrast so you can see how fuzzy it is.
If you saved it as a GIF or PNG file type then it would be crystal clear.
 

    E

    EDA_hg81

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Apart from the nasty schematic quality, I see this points:

- There are more poles (low-pass functions) in the circuit, e. g. 132 kHz (C4/R5) at U1.
- the OP output load is much to high. Fortunately, your are simulating only, otherwise you would most likely destroy the device or at least burn your fingers.

I suggest, that you start with a Linear application circuit, that can be expected to have meaningful dimensioning. Furthermore, a hand calculation of currents and power losses at some parts wouldn't be a bad idea, to my opinion, e. g. for the 2 x 15 ohm voltage dividers. Please consider also that high speed OPs are able to source high output currents and don't have a safe current limit like a LM741.
 

    E

    EDA_hg81

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here is the schematic in GIF format.


https://obrazki.elektroda.pl/69_1221399414.gif

Added after 12 minutes:

FVM.

Thank you very much for your ideas.

Added after 12 minutes:

FVM,

You are right.

The C5 and another C4 made this problem.

The reason why put them is for preventing oscillation.

How I can prevent oscillation? R1 and C1 is the dumper for anti oscillation too.

Do you have any suggestion?

Thank you so much.
 

The high speed OPs are usually stable with sufficient low feedback resistors. If a higher resistance level is needed for some reason, you can adjust a feedback capacitor to the minimum needed value, which would be below 1 pF in many cases.

The RC loads shouldn't be necessary in normal circuits, but may be needed sometimes, e. g. with capacitive loads. They are considerably decreasing the effective GBW, however. A resistive load isolation is the better alternative, if applicable. It's a good way, to treat longer PCB traces as transmission lines. E. g. a 70 ohm impedance trace to a distant circuit function is connected through a 68 ohm series resistor at the source. With a resistive load, this value is calculated into the load network.
 

    E

    EDA_hg81

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I have no idea.

I transfered schematic from PDF file.

Added after 1 minutes:

FVM,

Thank you so much for your valuable idea.
 

You possibly get a better quality when exporting a bmp file from TINA and converting it to gif.
 

    E

    EDA_hg81

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Sometimes saving a schematic as a GIF fike type results in a grid of dots all over it. Saving as a PNG file type is always perfect.
 

    E

    EDA_hg81

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