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Mentor Graphic: Project Porting to another SoftWare (50pt)

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sadid

sadid

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I've Design my project in Mentor Graphics/FPGA Advantage Package.........it's a really good S.W.
but now I need to implement These modules in my design using Mega functions and IPs......:
1.One or Two Soft Core
2.an CAM/RAM Memroy
3.Ethernet Interface
How can I port my project from FPGA Advantage to Quartus or ISE?
or How can I implement these IPs in my design?
or any suggest that might help....
Thank.
 

Re: Mentor Graphic: Project Porting to another SoftWare (50p

sadid said:
/.../How can I port my project from FPGA Advantage to qu(at)rtus or ISE?
Click to expand...
if I understand your question correctly, you should:
- create your project with so-called black-boxes which are
'place holders' for ise/quartus specific macros;
- add an attributes 'black box' for the modules if your tool requires it
[most probably yes];
- compile to generate an input for ise/quartus place&route and assembler;
[verilog netlist for instance]
- generate with ise/quartus required memories, interfaces [the body of your
'black boxes'];
add the netlist and tool [ise/quartus] specific macros [coregen/megawizard] to
your project and compile;

black box is an entity/module with ports declarations only, without any body;
[without any logic]
---
 

My Design in FPGA Advantage contains some component it has both entity and architecture...
I don't think that this approach is practical....do you have a related experience?
in addition I have a choice re-design my component in Quartus II v9 currently I've design my entity/architecture but I'm searching for faster approach...
 

Re: Mentor Graphic: Project Porting to another SoftWare (50p

sadid said:
/.../I don't think that this approach is practical/.../
Click to expand...
it's a standard flow when:
1.you have to generate a loadable fpga image;
2.you use a third party synthesis software;
3.your design contains any vendor specific module
[pll/lvds/mamory...] which you can not describe in verilog/vhdl
and it's not in the software library;
if any of the above items is not true you do not have to follow
the flow;
---
 

    sadid

    sadid

    Points: 2
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Thank j_ander so I can generate a loadable image with FPGA Advantage.......then import it to Quartus II and add required modules to it and generate final image...is it true? is it possible?
 

Re: Mentor Graphic: Project Porting to another SoftWare (50p

sadid said:
I can generate a loadable image with FPGA Advantage/.../
Click to expand...
not exactly;
you can generate a netlist with your tool, not an fpga image,
the netlist has to be imported to quartus and merged with altera macro(s);
---
 

Re: Mentor Graphic: Project Porting to another SoftWare (50p

in the HDL designer: in the right pane you can find the TASK pane: invoke xilinx core generator (or qu(at)rtus core generator).
choose then the library you need to create your IP then click Invoke core generator.
you will find a wizard that guide you with the available IPs. choose your IP then go in the other wizard steps.....
and tell me please if this is sufficient or not, also tell me if you faced any problems.
 

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