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State machine problem in Quartus - Please help

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ktsangop

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Hi everybody!

I have a verilog design compiled in Altera's quartus 7.2 web edition.
The design has the following state machine (the whole file is attached also) :
Code: 
[i]...
reg [2:0] idest_addr;
...
		case (idest_addr)
		3'b000 : r_out=data_in; 	
		3'b001 : e_out=data_in;  	
		3'b010 : n_out=data_in;	
		3'b011 : w_out=data_in;	
		3'b100 : s_out=data_in; 	
		3'b101 : e_out=data_in;	
		3'b110 : s_out=data_in;	
		3'b111 : w_out=data_in;	
		default : r_out=data_in;
		endcase
...[/i]

After compilation and after trying to simulate the design using quartus' simulator tool, i used node finder to add the idest_addr to my waveform file.
That's when i realised that the reg idest_addr (which is 3 bits wide) was represented as 8x1-bit wide registers with names 000,001,010...etc.

question 1 : Is this normal??Does this affect my design or is it just the way quartus represents state machine registers?

question 2 : My real problem is that one of those 8 registers is kind of stuck at 1. It gets 0 only when it is supposed to be 1!! :) (please take a look at the following image)

I've tried a few things but couldn't solve it.

Please guys take a look at my verilog file and give any suggestions.

Thanks in advance!
:)
 

ktsangop said:
/.../ realised that the reg idest_addr (which is 3 bits wide)
was represented as 8x1-bit wide registers/.../
Click to expand...
1.if you search logs of quartus you should find a message
that your state machine is coded as 'one-hot';
what is preferred coding method in fpga world;
one-hot means one register for each state, each state
is coded as one register 'ON' others 'OFF';
so - 8 states gives 8 flip-flops;

2.probably your fsm 'idest_addr' after reset should be in
in state "00..0" - but the first state in 'one-hot'
should be "00..01" so after reset all registers get value '0'
but the 'first' register has an inverter;

everything seems to be ok;
---
 

    K

    ktsangop

    Points: 2
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State machine problem in qu(at)rtus - Please help

Thanks a lot!
I think i understand how it works although it seems a little strange.

So in the end, is this going to work properly or am i going to have to change the first state to "001" instead of "000"??

The only thing that bothers my is that if i have to do this, i will also have to increase the width of idest_addr to 4 bits. The rest of my design will be also affected and so on...

Anyway, thanks again j_andr! You've been really helpful!!
 

State machine problem in qu(at)rtus - Please help

I suggest to read the State Machine Processing paragraph of the Quartus II Handbook, Vol 1, Chap. 8 Quartus II Integrated Synthesis, Quartus II Synthesis Options.
 

    K

    ktsangop

    Points: 2
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State machine problem in qu(at)rtus - Please help

Thanks a lot FvM!!
Finding this by myself would be quite impossible, considering the hugeness of the quartus handbook...!
:)
 

ktsangop said:
/.../although it seems a little strange/.../
Click to expand...
why strange ?
'one-hot' needs more registers but less combo logic and
usually less interconection between cells;
modern fpga are rich of flip-flops, the bottelneck is
- first routing resources, then logic gates;
and FSM coded as 'one-hot' are faster;
/.../have to change the first state to "001" instead of "000"?
Click to expand...
you do not need to change anything - but after reading suggested by
FvM document you probably know it yourself ;)
[quartus synthesis tool is pretty good contrary to ise ...]
--
 

    K

    ktsangop

    Points: 2
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Finding this by myself would be quite impossible, considering the hugeness of the qu(at)rtus handbook...!
Click to expand...
I agree. I also had to learn, that the Quartus II Handbook is the book that contains nearly any relevant information related to the tool. In course of time, you understand it's systematic (if any) and know where to find a topic. I'm often using Acrobat text search with the Handbook by the way, the same with device handbooks and IP user guides.
 

    K

    ktsangop

    Points: 2
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