How to establish synchronization in serial data transfer?

Hi all,
I'm finfding difficulties to understand how synchronization can be established in serial data transfert.
Suppose that we have a Transceiver and a Receiver (or Serializer/Deserialize). When the former send a stream of bits the latter is supposed to be able to receive them. Obviously the two devices have each a PLL running at the same frequency F. The receiving mecanism is ok only when the two PLLs synchronize themselves. In the documentation, I found that this is done by sending a set of 0 and 1 (from the Transceiver to the receiver) and this data is used by the CRD circuitery. I have two questions:
1- When there is no data to send, does the transceiver sends continusuosly the set of data 0 and 1 in order to maintain the PLLs synchronized, thus ready to ensure a new data transfert ? Actually the PLL requires a very long time (too many cycles) to lock and I see only this solution to have a good performance in terms of latency.

2- If the reply is no I mean that this synchronization using 0 and 1 bits are used only when we'd like send data, how long we do that and how the receiver recognize that this received signals are for synchronization and not data ?

Thanks in advance.

Re: Synchronization

1.
Usually the data signal is coded to insure transitions and avoid long sequences of 0s or 1s.
Also a scrambler at TX, descrambler at RX is used to randomize the transmitted data.

The transmission is continous if the data link is synchronous - even if no data is to be transmitted a dopping seq is transmitted.
If the transmission is asynchronous when there is nothing to send the TX is off

2. The synch pattern duration - also named PREAMBLE depends on the time required by the PLL to lock. Ex Ethernet 7 bytes.
Generally in asynchronous transmission the time needed for synch needs to be minimized to have a good efficiency. Thus PLL lock time is short and the jitter obtained quite high.
For synchronous transmission the timed needed can be quite long - the synch only hapens once at startup. PLL lock time high, low jitter. The strategy to detect lost synch and reacquire synch is more complex.