Help with a mux-like design

Hi everyone!
I am stuck. I need some help with a mux...

I want to design a mux that has the following specs.

- 5 inputs (one bit wide ) & one ouptut (one bit wide)
- All input channels have an enable signal. (Just to declare that the input is ready to transmit)
- At any given time the output is equal to one of the inputs.
- If only one input is enabled then it is driven to the output
- If more than one inputs are enabled then they are driven to the output in a round robin way. eg input1 sends bit by bit a fixed amount of bits to the output and then the next enabled input channel eg input2 sends its data to the output and so on...

It looks almost impossible to code it only with if else branching conditions so...
i would appreciate any ideas.

Thanks in advance!

If your design is intended to work similar to an UART multiplexer, your specification is very incomplete to my opinion. If you can expect each input to send data at any time, the design must be able to buffer data or it get lost.

If the inputs are not expected to send simultanously respectively at any time, the multiplexer has to know about there send action. How?

Even if the multiplexer would simply scan the inputs without caring for the momentary input states, it needs a timer. You didn't tell a word regarding timing specification. One could expect a state machine to be implied, generally.

You may have difficulties to express the design using a HDL language. However, at present time, you should start to draw timing diagrams, that define the expected behaviour. This doesn't require particular logic programming knowledge, just thinking clearly about the design purpose and possible operation.

You are totally true. Specs are incomplete. Sorry about that but i am a verilog noob.
The only things i can add are:

- inputs are buffered. In fact input data come from shift registers.
- There is a master clock and all operations(not sure about this one) occur at the posedge of this clock
- At every posedge clock, the mux checks if any of the inputs are ready to send data.
- The input that is selected to transmit data sends all the bits of the register to the output.
- In the meanwhile the other inputs wait
- When transmission is complete the mux allows the next "ready to send" input to send its data.

I suppose that the check for the inputs that are ready to transmitt should be done using a shorter time clock.?????

Sorry about the incoherence of my description but it's more like a do and check project rather than a specified one.

If you could come up with any suggestion i would be very thankful. If it's still too unclear no problem.
I'll try to come back with some serious specs

Thanks again.

Sounds much clearer already. To proceed, the handshake signals related to the individual signal sources should be clearly defined, also a possible required gap between two serial data words has to be defined.

I don't think, that a higher clock frequency would be needed to process the requests, a rotating priority scheme could also have a result within a single clock cycle.