Floor Planning Issues

Can someone let me know, what are the typical issues faced during floor planning decision of a mixed signal chip.

Please point to me a link / file tutorial.

I would appreciate if it does not include any tool details, as i am a front end designer.

Main concepts:

- Identify noisy and noise sensitive blocks in order to place them as far as possible. ALso, the idea is to join all noisy blocks together.
- BOnd pads placement.
- PWR and GND main lines preliminary path plannification.
- Clock or noisy lines path identification (if possible the idea is to make them as short as possible by placing their generating blocks according this)
- Carefull identification and placement selection of teh component with higher power dissipation, in order to know how thermal gradients will be in your chip.

ANd many many other things, but with this first ones you'll have a more than good starting point for your design...

Hope this helps.