Explanation of the cycle steal process from XAPP617 application notes

 -- Capture potential first bit data, double sampling to remove metastability
   PROCESS (NREC_CLK, XRESET)
   BEGIN
      IF (XRESET = '0') THEN
         FQ <= (others=>'0');    
      ELSIF rising_edge(NREC_CLK) THEN
         FQ <= DF;    
      END IF;
   END PROCESS;

   -- Move falling edge samples into the rising edge clock domain using latches (cycle steal)
   PROCESS (NREC_CLK, FQ, XRESET)
   BEGIN
      IF (XRESET = '0') THEN
         FL <= (others=>'0');    
      ELSE
         IF (NOT NREC_CLK = '1') THEN
            FL <= FQ;    
         END IF;
      END IF;
   END PROCESS;

   -- FL metastability flops
   PROCESS (REC_CLK, XRESET)
   BEGIN
      IF (XRESET = '0') THEN
         FO <= (others=>'0');    
      ELSIF rising_edge(REC_CLK) THEN
         FO <= FL XOR "01010101";    
      END IF;
   END PROCESS;