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Which kind of buffer should I use for increasing the fan out

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Clock

I have used a input clock( 50MHZ) to generate another clock( 250KHZ) by using simple counter.

Which kind of buffer I should use for increasing the fan out ability of this 250KHZ clock?
The FPGA I am using is Spartan 3.
Thanks.
 

Re: Clock

I think, any CMOS logic would fit, depending on the voltage level it could be e. g. HCT (5V) or LVC (3.3V). But FPGA outputs have high drive capability, a buffer must not necessarily be used, except for driving higher voltages or to protect the FPGA, if the output is off-board.
 

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    EDA_hg81

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Clock

If you are talking about clock fanout inside the FPGA, you can buffer the counter output with a BUFG primitive, or one of its relatives (see your ISE Libraries Guide). That global clock buffer drives a low-skew clock net throughout the FPGA.
 

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    EDA_hg81

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Re: Clock

Hello,

Don't use any divider to divide the clock, because there is always a propagation delay will be there.

You can use internal PLL provided by the FPGA tool and the resources available within the FPGA.

If u need more info don't hesitate to ask me.

Thank you,
N.Muralidhara
 

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    EDA_hg81

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Clock

The propagation delay introduced by a divider is harmless for many applications.

Spartan-3 doesn't provide any PLLs. It provides DLLs instead. The DLL doesn't go down to 250 kHz.

Counters don't add significant phase noise, whereas PLL and DLL do. That's important in some applications.
 

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    EDA_hg81

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Re: Clock

echo47 said:
If you are talking about clock fanout inside the FPGA, you can buffer the counter output with a BUFG primitive, or one of its relatives (see your ISE Libraries Guide). That global clock buffer drives a low-skew clock net throughout the FPGA.
Click to expand...

Now this is what I've been looking for. :D

Can somebody please tell me how to instantiate/define BUFG primitive to use in similar situation described above?

Thanks
 

Re: Which kind of buffer should I use for increasing the fan

Code: 
Library UNISIM;
use UNISIM.vcomponents.all;
-- BUFG: Global Clock Buffer (source by an internal signal)
-- All Devices
BUFG_inst : BUFG
port map (
O => O, -- Clock buffer output
I => I -- Clock buffer input
);
-- End of BUFG_inst instantiation
 

Thanks for your reply kvingle.

Can you please tell me where can I find related document to gather more details for above the module?
 

Re: Which kind of buffer should I use for increasing the fan

sure! its there in your xilinx installation directory. In my case...

D:\Xilinx\10.1\ISE\doc\usenglish\books\docs\spartan3e_hdl.pdf


here you will get info on all the resources available in given FPGA family and their usage and other howtos.(there are different directories for different families.
 

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