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How to solve Setup and Hold violation without reducing FPGA clock frequency?

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vlsi_freak

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Hi.

Set up and hold violation is discussed a lot in this forum.

Its a good approach to minimize clk frequency to over come set up violation,

and inserting clk buffers to overcome hold violation.

Suppose i cant reduce my clk frequency in FPGA (not ASIC), is there any other method to overcome Setup and Hold violation.

Plz share ur valuable ideas.

Thanks
 

FPGA Timing

i think u can reduce the frequency by writing frequency divider HDL code.
 

Re: FPGA Timing

Hi Praveen

Suppose i need to run my design in the same frequency.

wht shuld i do to remove set up and hold time violation.

wht are the methods to remove setup and hold time violation.

Thanks
 

FPGA Timing

When you reduce a little bit the frequency constrain, it will normaly work.
 

FPGA Timing

If you still want to keep the same frequency even there are setup violations, probably, you could redesign your circuit in the path where it has setup violations.
 

Re: FPGA Timing

I think Hold timing the router should be able to solve. However for setup time violations you should add pipeline in timing critical paths. If you really have function which cannot split with a pipeline, writing your RTL in boolean equation (of-course the optimised ones) does help many times.

Parikshit
 
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    vlsi_freak

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    Anklon

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Re: FPGA Timing

Hi..

Is there any option to add Buffers to avoid hold time violation in FPGA.
If router failed to fix hold time violation, can a user fix it manually.

Thanks
 

Re: FPGA Timing

Rewrite your HDL code.
 

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