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pls help to analyze this circuit

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Fei

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Hi, friends

Do you know the name of this circuit?
How to analyze it?
Thank you.
 

It is a inverter with hysteresis.
 

Yes its an inverter with hyteresis, because here output not only depends on input but also on previous output, which providing the bias for an inverter.
 

Yes its an inverter with hyteresis, because here output not only depends on input but also on previous output, which providing the bias for an inverter.


But the output of this inverter is not rail-to-rail swing. It is changed from Vthn to Vdd-lVthpl.
And when Vin is 0 or Vdd the output switces to high-impedance state.
 

But this type buffer will have serious Process , Voltage , Temperature effects.
And then is hard to guarantee performance !!
 

Fom said:
Yes its an inverter with hyteresis, because here output not only depends on input but also on previous output, which providing the bias for an inverter.


But the output of this inverter is not rail-to-rail swing. It is changed from Vthn to Vdd-lVthpl.
And when Vin is 0 or Vdd the output switces to high-impedance state.

You are saying the ideal case, right?
I have done a dc simulation on this circuit.
When the input voltage is lower than the Vthn the output voltage drops linearly from Vdd.

May I regard this circuit as a gain-controlled amplifier?
 

When the input voltage is lower than the Vthn the output voltage drops linearly from Vdd.

DC analisys can show not real result. More exactly it is real but for infinity time. Try transient.
 

    Fei

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