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What is meant by BC,WC in STA

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phutanesv

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what is meant by wc

Dear dude,

So far i have learnt is bc,wc are the type of STA using prime time,

what is also meant by OVC- (On- Chip-Variation)

Actually what are this.

Need a clear explanation

phutanesv
 

slew propagation primetime

The analysis modes can be classified by different ways. The way timing arcs are calculated from clock arrival and Slew propagated across the path. Let me explain with PT as signoff tool. It may be applicable for other tools too, but not yet worked on timing sign off tools.


To make clear about this, let us consider the single OC also with BC-WC and OCV.

Single OC :
At Launch clock path: Late clock, max delay in clock path ,No derating and single OC.
At Data path : Max delay, Single OC,No derating.
At Capture clock path : Early clock, min delay in clock path, single OC. no derating.

slew propagation : max slew is propagated irrespective setup or hold.

BC-WC :
At Launch clock path: : Late clock,max delay in clock path, late derating,WC OC.
At Data path : Max delay, WC OC, late derating.
At Capture clock path : Early clock, min delay in clock path, WC OC. early erating

slew propagation : max slew is propagated during setup analysis and min slew propagted during hold analysis.

OCV :
At Launch clock path: : Late clock,max delay in clock path, late derating,WC OC.
At Data path : Max delay, WC OC, late derating.
At Capture clock path : Early clock, min delay in clock path, BC OC. early erating

slew propagation : During setup analysis, max slew for data launching path and min slew for data capturing path. During hold analysis, min slew for data launch path and max slew for data capture path.

Single OC is used before layout,since design was not extended for clock tree structure. BC-WC is recommended to test both corners after layout. but OCV will account more pessimisam to account for PVT variations across the die.

Hope you understood.

Regards,
Sam
 

    phutanesv

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slew propagation wiki

BC- best case, WC-worst case
 

what is min delay in max corner during sta

i know that PTV is very important with BC(bset-case) and WC(worst case) .
 

best corner pvt slew propagation

when you want to analyse your design with min delay of all cells and nets then you can use best_case. if you want to check your design with max corner then you can user worst_case. and when you want to check both variations in same analysis then you can use ocv
 

PrimeTime offers three analysis modes with respect to operating conditions, called the single, best-case/worst-case, and on-chip variation modes:

*

In the single operating condition mode, PrimeTime uses a single set of delay parameters for the whole circuit, based on one set of process, temperature, and voltage conditions.
*

In the best-case/worst-case mode, PrimeTime simultaneously checks the circuit for the two extreme operating conditions, minimum and maximum. For setup checks, it uses maximum delays for all paths. For hold checks, it uses minimum delays for all paths. This mode lets you check both extremes in a single analysis run, thereby reducing overall runtime for a full analysis.
*

In the on-chip variation mode, PrimeTime performs a conservative analysis that allows both minimum and maximum delays to apply to different paths at the same time. For a setup check, it uses maximum delays for the launch clock path and data path, and minimum delays for the capture clock path. For a hold check, it uses minimum delays for the launch clock path and data path, and maximum delays for the capture clock path.
 

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