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Set Up Time Violation

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ryusgnal

ryusgnal

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muticycle path in asic

Can anybody help me with the circuit below. Is there any setup violation for the circuit? If yes, what is setup time violation? What should I do to fix it?

**broken link removed**
 

Set up time in nothing but the time period for which the data input to the flop should be valid before the transition of the clock occurs... i.e normally rising edge of the clock...

I think the data here is in sufficient... you have to mention the clock period and the set up time of the flop... you can avoid set up time violation by increasing the clock period... the condition to avoid set up time violation is
Tclk>= Tclk-q + Tsetup + Tcomb - Tskew
 

    ryusgnal

    ryusgnal

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Tclk+Tskew(min)>=Tclk-q(reg1)+Tcomb(max)+Tsetup(reg2)
 

    ryusgnal

    ryusgnal

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deh_fuhrer said:
Tclk+Tskew(min)>=Tclk-q(reg1)+Tcomb(max)+Tsetup(reg2)
Click to expand...

May i know any referrence of this?
 

setup violation is there
using the equation
Tclk1+Tclktoq+Tcomb<=Tclk2+Tperiod-Tsetup

Added after 2 minutes:

setup violation is removed using the decrasge the data path delay and increment the clock period .using this one u remove the setup violation

Added after 1 minutes:

vamsi
 

ryusgnal said:
deh_fuhrer said:
Tclk+Tskew(min)>=Tclk-q(reg1)+Tcomb(max)+Tsetup(reg2)
Click to expand...

May i know any referrence of this?
Click to expand...

Digital Integrated Circuits
A Design Perspective
A Prentice-Hall Publication by Jan M. Rabaey

Added after 14 seconds:

**broken link removed**

Added after 47 seconds:

DONT FORGET TO PRESS THE HELP BUTTON..
 
U can also remove this setup violation by giving muticycle path ......
that probably depends on design ....
 

what are the clk period, Tcq, Tnet and setup time
 

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