How fast a pad can be???

Is it possible to export/import a clock signal of some 3GHz from/to a chip in a 0.13um technology?
If so, what cautions should be taken for the I/O circiut, say,the buffer,PAD etc...

it is a bit difficult for cmos process. the buffer has a delay of nano seconds already.

almost impossible for IO, an pad usually have ~1pf cap, plus package and routings, 3G signla can easily be degraded to zero.

It is not just about the I/O pad cap (which can be about 3-6pF)....
Can 130nm technology circuits function at 3GHz?? I really doubt that... In 90 or 65nm, yes.. But in 130nm??
Has anybody been able to design a custom flop or a VCO which can switch at 3GHz on 130nm?

I think 3GHZ is diffect in 130nm, we use 1.5Ghz pads design by IBM it working well , and someother
company 1.5Ghz pads has some question.

Yes, you should be able to with no problem. The pad capacitance will be 100fF or less. Use a low capacitance ESD, which should give you 1000 to 1500V HBM. I would start with a basic CML output buffer and then there are various design techniques that allow you to broadband this output buffer. For 0.13u, you should be able to achieve 5 GHz with no problem. I was able to get 3 GHz (upper 3dB) on a 0.18u CMOS technology without using any broadbanding techniques on a CML output driver. One more thing, make sure that your bond wire inductance doesn't go over 1nH.

Added after 3 minutes:

Yes, you should be able to with no problem. The pad capacitance will be 100fF or less. Use a low capacitance ESD, which should give you 1000 to 1500V HBM. I would start with a basic CML output buffer and then there are various design techniques that allow you to broadband this output buffer. For 0.13u, you should be able to achieve 5 GHz with no problem. I was able to get 3 GHz (upper 3dB) on a 0.18u CMOS technology without using any broadbanding techniques on a CML output driver. One more thing, make sure that your bond wire inductance doesn't go over 1nH.

Hi,krashkealoha,then what do you mean by CML,plz?

CML stands for Current mode logic... Logic switching is based on current switching.. The only disadvantage in this kind of logic is that static power dissipation is very high.. But noise is greatly reduced..

@krashkealoha, what was the voltage domain you used to achieve 3MHz - 1.2 or 3.3?? I guess, CML is the determining factor there rather than the voltage... but still was curious to hear from you..
I doubt whether this could be done through conventional switching techniques...

Hi
You shoul use off-chip matching circuit and on chip clock receiver

The supply voltage was 1.8-2.5V for the 0.18u CML driver, which used standard design techniques to achieve 3 GHz bandwidth. We were also able to achieve 8-9 GHz bandwidth (upper 3dB) for a CML output driver using a 0.5u SiGe BICMOS (2.5-3.3V) technology using broadbanding circuit techniques.

Let me change my previous statement of having bondwires of less than 1nH. I remember one part that we were able to achieve 5GHz bandwidth with long bondwires (2.5-3nH inductance).

For a CML output, your output pole will be f = 1/(2*pi*R*C). Your R value is 25 ohms (50 internal in parallel with the 50 ohm output termination). Your C value is your pad capacitance.

Hi
I think the bandwidth is not needed to receive clock
You can receive one harmonic only and produce more on chip using clock receiver
So the narrow bandwidth matching technique can be used off-chip
We have experience translating up to 6GHz clock from pcb to IC (implemented in 0.18u digital process) Pads were ESD protected