katrin
Full Member level 1
vdd and vss what does it mean
In the standard ESD circuit of my CMOS designkit
there are two positive and negative supply voltages respectively---just Vdd(pad) and Vdd2(core), Vss1(pad) and Vss2(core). and it is also required that Vdd(pad) and Vdd2(core) should not be connected together , the same for Vss. I am quite confused about that, why there are two Vdd and two Vss?
But on the other hand, in my circuit design, I only have one positive supply voltage Vdd and one negative supply voltage Vss. Therefore how can I have two different Vdd and Vss for the ESD protection cell?
In the standard ESD circuit of my CMOS designkit
there are two positive and negative supply voltages respectively---just Vdd(pad) and Vdd2(core), Vss1(pad) and Vss2(core). and it is also required that Vdd(pad) and Vdd2(core) should not be connected together , the same for Vss. I am quite confused about that, why there are two Vdd and two Vss?
But on the other hand, in my circuit design, I only have one positive supply voltage Vdd and one negative supply voltage Vss. Therefore how can I have two different Vdd and Vss for the ESD protection cell?