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why are two different Vdd and Vss in ESD standard cell?

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katrin

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vdd and vss what does it mean

In the standard ESD circuit of my CMOS designkit

there are two positive and negative supply voltages respectively---just Vdd(pad) and Vdd2(core), Vss1(pad) and Vss2(core). and it is also required that Vdd(pad) and Vdd2(core) should not be connected together , the same for Vss. I am quite confused about that, why there are two Vdd and two Vss?

But on the other hand, in my circuit design, I only have one positive supply voltage Vdd and one negative supply voltage Vss. Therefore how can I have two different Vdd and Vss for the ESD protection cell?
 

I think, usually VSS1 and VSS2 connect together in borad's input power connector (not near chip power pins). and depend on your circuit each of VDD could be filtered using LC filter, and isolated from each others (i mean AC isolation, eg. noise, spike ...).
 

ESD stress current can cause large IR drop. With voltage drop on ESD zapping element this can destroy i/o buffer in core. That is why supply are separated on power and "clear" with additional protection on "clear" side. Both power and "clear" supplies must be connected only on their PAD. Never mix this supplies with core supply.
 

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    katrin

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Maybe the two VDDs and VSSs are bonded together.
 

DenisMark said:
ESD stress current can cause large IR drop. With voltage drop on ESD zapping element this can destroy i/o buffer in core. That is why supply are separated on power and "clear" with additional protection on "clear" side. Both power and "clear" supplies must be connected only on their PAD. Never mix this supplies with core supply.
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does it mean Vdd(pad) and Vdd(core) can only be connected together via the Vdd power supply pad(only one Vdd power supply pad) (In the ESD protection device, I should not connect these two together)?

I just want to make sure about that.

thanks
 

You are right!!! Connect them only near PAD.
 

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    katrin

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Due to the concern of power noise.
 

Seperated supply PADs and ground PADs are used to isolate noise. For example, you need one VDD/VSS for digital circuit and another VDD2/VSS2 for analog circuit for SOC system. If they are shared, IR drop caused by switching of digital circuit will corrupt analog circuit operation.
 

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    katrin

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In the datasheet of ESD protection device, it is said: Vdd1 and gnd1 are the ESD-rails; Vdd2 and gnd2 are the power supply for the periphery ring.

Until now my understand is that I should connect two Vdd together via the Vdd pad, the same for Vss. And my chip can only has one Vdd pad and one Vss pad.

But what about different Vdd and Vss for analog and digital circuits? they are just provided by two different Vdd pads?

It reminds me that my design also had both analog and digital parts, but they are powered by a single supply voltage. When we use a single supply voltage for the mixed signal IC, are there any consequence?
 

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