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state machine problem in VHDL..

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L

leoren_tm

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i have a problem with my clk on state machine..
i have a fix clk of 25Mhz, with this speed its imposible for me to display every state.
i hava a 4 state implemetation..
thats is a for 7 segment display on xinlinx spartan3,
how do i code it??
.................................
ex...i have to count 4096 rise of clock before it will jump to other state..
Code: 
if(.......)then
count=count+1
end if
 

generate a CE based on 4096 count and use this CE in the state machine.

CE <= '1' when count = 4096 else '0'.

state mchine use this CE as enable for state transition.
 

CE stand for??
yha...i need to count 4096 rise of the clock before it will change a state..
can you explain more about CE?
 

leoren_tm,

you can use your quoted code and bansalr logic. For example


if (clock 'event and clock = '1') then
count <= count + 1;
end if;

--with this line, you can jump or signalize that your state already finish. The
--other part about 7-seg display, you need to give us more detail
CE <= '1' when count = 4096 else '0';

Best regards

Breno
 

Hi

CE is chip select/enable flag which will go high when the coutner reaches the max value...

This in turn will trigger ur state machine....
 

25MHZ/4096=6.103KHZ you still not be able to see your display. Please give more details what exactly are trying to impliment
regards
 

i already divided my clock..i count 4096/2...
her is my code for it.
Code: 
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY clk2 IS
PORT (
	clk : IN STD_LOGIC;
	clkkj : OUT STD_LOGIC);
END clk2;

ARCHITECTURE a OF clk2 IS
BEGIN
PROCESS (clk)
VARIABLE cnt : INTEGER RANGE 0 TO 4096;
BEGIN
	IF (clk'EVENT AND clk = '1') THEN
	cnt := cnt + 1;
	END IF;

	IF (cnt >= 2048) THEN
	clkkj <= '1' ;
	
	elsif (cnt >=4096) then
	cnt := 0 ;
	ELSif (cnt <= 2047)  then
	clkkj <= '0';
	
	END IF;

END PROCESS;
END a;
and i got a problem on my state....for clarification , im using a xinlinx spartan 3 for my implementation..
her my other code
Code: 
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY stop IS
PORT(
pb : IN STD_LOGIC;
input : IN STD_LOGIC_VECTOR(1 downto 0);
q : OUT STD_LOGIC_VECTOR(10 downto 0));
END stop;

ARCHITECTURE behavior OF stop IS

COMPONENT  clk2 
PORT (
	clk : IN STD_LOGIC;
	clkkj : OUT STD_LOGIC);
END COMPONENT;

TYPE STATE_TYPE IS (s0, s1, s2, s3);
SIGNAL state: STATE_TYPE;



SIGNAL CLKKJ,CLK : STD_LOGIC;

BEGIN
DUT: CLK2 PORT MAP(clkkj=>clkkj, CLK=>CLK);
PROCESS (clkkj)


BEGIN

IF (input="00") THEN
--wait until ;
IF clkkj'EVENT AND clkkj = '1' and pb'event and pb='1' THEN

CASE state IS

WHEN s0 => --IF (input="001") THEN
state <= s1;
q <= "01001000111";


WHEN s1 => --IF (input="001") THEN

state <= s2;
q <= "11100001011";


WHEN s2 => --IF (input="001") THEN

state <= s3;
q <= "11000101101";

--END IF;

WHEN s3 => --IF (input="001") THEN

state <= s0;
q <= "10011111110";


END CASE;
END IF;
END IF;
END PROCESS;
END behavior;
suppose to be, it will display a "StoP" word..
the 4 less significant bit on q, will be use as enable an disable for the common anode, sevensegment display,
and the 7 most seignificant would display "s,t,o,P"
pls help me ...

Added after 5 minutes:

im kind of confuse..
"ph" is a push button for my edge triger clock....
it will function as a flipflop..
if my input will be change, it should not affect my seven segment display.....
only if my ph is push, then it will change...
..........uhmmmmmmmmmmmm
a want to display 4 defirent system..
:"stop"
"sys1"
"sys2"
"sys3"
thats why i have and input of two bits.....for 4 posivility..
hop you understand my problem...

Added after 3 minutes:

and....
uhmmmmmmmmmmmmmmm
on the "process" what is the importance of the sensitivity list??
if the condition on the input If will be change, will it affect my state??

Added after 1 minutes:

heir my sample state
 

Ok you need this

you need to have two process one is for switching states in the state machine another to do the actual decoding...

Onother think for you clock divider depending on the FPGA platform what you are using it might not work well...


Think ablut using PLL there or do different way of sync

look here thre are few articles about state machine design
www.sunburst-design.com
 

im doing a VHDL programing...
no other choice...
please help me on the flipflop the pushbutton
 

this is my resulst...i got red on my output..pls help me
 

you need to have two process to run you machine,

also you do not have init state for you machine, how complier will figure out at what state yout machine should start, read the papes what I suggested in my early posting
 

uhmm...i think my code in VHDL run....just a few change...
did you understand my code??
 

your outputs is showing XXX, I think you test bench is running but not actual UUT.

Think from this side when you power up your sytem, which state your machine will take?
 

uhmmm....i think its a dont care sitution...
ok..ill have to redo it..
ill post a new code that is running...
 

Checkout this one!
Hope this helps!

Code: 
library ieee; 
use ieee.std_logic_1164.all; 

entity stop is 
port(
  clk   : in std_logic;
  rst_n : in std_logic;
  pb    : in std_logic; 
  input : in std_logic_vector(1 downto 0); 
  q     : out std_logic_vector(10 downto 0)); 
end stop; 

architecture behavior of stop is 
  type state_type is (s0, s1, s2, s3, s4); 
  signal state, state_nx : state_type; 
  signal pb_filter : std_logic_vector( 7 downto 0);
  signal pb_r, pb_rr, pb_rising : std_logic;
begin
  process (clk, rst_n)
  begin  -- process
    if rst_n = '0' then                 -- asynchronous reset (active low)
      state <= s0;
      pb_r <= '0';
      pb_rr <= '0';
    elsif clk'event and clk = '1' then  -- rising clock edge
      state <= state_nx;
      pb_filter <= pb_filter(6 downto 0) & pb;
      pb_r <= pb_filter(0) and pb_filter(1) and pb_filter(2) and pb_filter(3) and pb_filter(4) and pb_filter(5) and pb_filter(6) and pb_filter(7);
      pb_rr <= pb_r;
    end if;
  end process;

  pb_rising <= pb_r and (not pb_rr);

  process (state, input) 
  begin
    state_nx <= state;
    if pb_rising = '1' then
      case state is
        when s0 =>  state_nx <= s1; 
        when s1 =>  state_nx <= s2; 
        when s2 =>  state_nx <= s3; 
        when s3 =>  state_nx <= s4; 
        when s4 =>  state_nx <= s1; 
      end case;
    end if;
    
    case input is
      when "00" =>
        case state is   -- gfedcba
          when s0 => q <= "00000001111";  -- blank display
          when s1 => q <= "01011010111";  -- display S
          when s2 => q <= "11110001011";  -- display t
          when s3 => q <= "10111001101";  -- display o
          when s4 => q <= "11100111110";  -- display p
        end case;
      when "01" =>
        case state is   -- gfedcba
          when s0 => q <= "00000001111";  -- blank display
          when s1 => q <= "01011010111";  -- display S
          when s2 => q <= "11011101011";  -- display y
          when s3 => q <= "01011011101";  -- display S
          when s4 => q <= "00001101110";  -- display 1
        end case;
      when "10" =>
        case state is   -- gfedcba
          when s0 => q <= "00000001111";  -- blank display
          when s1 => q <= "01011010111";  -- display S
          when s2 => q <= "11011101011";  -- display y
          when s3 => q <= "01011011101";  -- display S
          when s4 => q <= "10110111110";  -- display 2
        end case;
      when "11" =>
        case state is   -- gfedcba
          when s0 => q <= "00000001111";  -- blank display
          when s1 => q <= "01011010111";  -- display S
          when s2 => q <= "11011101011";  -- display y
          when s3 => q <= "01011011101";  -- display S
          when s4 => q <= "10011111110";  -- display 3
        end case;
      when others => q <= "00000001111";  -- blank display
    end case;
  end process; 
end behavior;
 

    L

    leoren_tm

    Points: 2
    Helpful Answer Positive Rating
WOW ..
THANKS FOR THE CODE...ill look at it..
ill post my code as soon as debug it,...
you got an advance code..
:D:D:D:D:D

THANKS A LOT[/code]
 

hir is my code...i already tested it on the xininx SPARTAN3.
and it works..but i think i did my code badly..
Code: 
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY main IS
PORT(
	input_old : in std_logic_vector( 1 downto 0);
	clk, pb : in std_logic;
	output : OUT STD_LOGIC_VECTOR(10 downto 0));
END main;

ARCHITECTURE struct OF main IS
TYPE STATE_TYPE IS (s0, s1, s2, s3);
signal state: STATE_TYPE;
signal clk_delayd : std_logic ;
signal input_new :  std_logic_vector(1 downto 0);
BEGIN

PROCESS (clk)
  VARIABLE cnt : INTEGER RANGE 0 TO 4096;
  BEGIN
  IF (clk'EVENT AND clk = '1') THEN
	cnt := cnt + 1;
  	IF (cnt >= 2048 and cnt < 4096) THEN
			clk_delayd <= '1' ;
   	ELSIF (cnt >=4096) THEN
			cnt := 0 ;
  	ELSIF (cnt <= 2047)  THEN
			clk_delayd <= '0';	
  	END IF;
  END IF;	
END PROCESS;

PROCESS (pb)
  BEGIN
  IF (pb'EVENT AND pb = '1') THEN
	input_new <= input_old;
  END IF;
END PROCESS;

PROCESS (clk_delayd, pb)
  BEGIN

  IF (clk_delayd'EVENT AND clk_delayd = '1') THEN

		IF (input_new = "00") THEN
					CASE state IS
					WHEN s0 => 
					state <= s1;
					output <= "01001000111";
					WHEN s1 => 
					state <= s2;
					output <= "11100001011";
					WHEN s2 => 
					state <= s3;
					output <= "11000101101";
					WHEN s3 =>
					state <= s0;
					output <= "00110001110";
					END CASE;
		ELSIF (input_new = "01") THEN
					CASE state IS
					WHEN s0 =>
					state <= s1;
					output <= "01001000111";
					WHEN s1 =>
					state <= s2;
					output <= "10001001011";
					WHEN s2 =>
					state <= s3;	
					output <= "01001001101";
					WHEN s3 =>
					state <= s0;
					output <= "10011111110";
					END CASE;
		ELSIF (input_new = "10") THEN	
					CASE state IS
					WHEN s0 =>			
					state <= s1;
					output <= "01001000111";		
					WHEN s1 =>			
					state <= s2;
					output <= "10001001011";		
					WHEN s2 => 
					state <= s3;
					output <= "01001001101";	
					WHEN s3 =>
					state <= s0;
					output <= "00100101110";
					END CASE;
		ELSIF (input_new = "11") THEN
					CASE state IS
					WHEN s0 =>				
					state <= s1;
					output <= "01001000111";			
					WHEN s1 =>			
					state <= s2;
					output <= "10001001011";		
					WHEN s2 =>				
					state <= s3;
					output <= "01001001101";			
					WHEN s3 =>			
					state <= s0;
					output <= "00001101110";		
					END CASE;
		END IF;
  END IF;
END PROCESS;
END struct;
 

not sure why do you need this for

ELSIF (cnt >=4096) THEN
cnt := 0 ;
ELSIF (cnt <= 2047) THEN
clk_delayd <= '0'

can you just say
else
clk_delayd < '0';
 

uhmm.....
i think it would be better if i specify it..
becuz i think ill will have a problem in implemting it, if i will not specify it...
and also i did have a problem on running it, with that condition...
uhmm..
thanks..
i think it would be better if i did that way..
can you give a sugestion on my clock??delay??
i think it was badly implemented!!
 

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