Problem with writing a code for a state machine on Xilinx

library IEEE; 
use IEEE.STD_LOGIC_1164.ALL; 
use IEEE.STD_LOGIC_ARITH.ALL; 
use IEEE.STD_LOGIC_UNSIGNED.ALL; 

---- Uncomment the following library declaration if instantiating 
---- any Xilinx primitives in this code. 
--library UNISIM; 
--use UNISIM.VComponents.all; 

entity bass2 is
  port ( wp  : out std_logic_vector (11 downto 0);
         wz  : out std_logic_vector (11 downto 0);
         bup : in  std_logic;
         bdn : in  std_logic);
end bass2;

architecture Behavioral of bass2 is
  type state_type is (flat, six, twelve, nsix, ntwelve);
  signal state, next_state : state_type;

begin

  process1 : process (bup, bdn)
  begin
    if (bup = '0' and bdn = '0') then
      state <= flat;
    elsif (bup = '1' or bdn = '1') then
      state <= next_state;
    end if;
  end process process1;


  process2 : process (bup, bdn)
  begin
    case state is
      when flat =>
        if (bup = '1' and bdn = '0') then
          next_state      <= six;
        elsif (bup = '0' and bdn = '1') then
          next_state <= nsix;
        end if;

      when six                    =>
        if (bup = '1' and bdn = '0') then
          next_state                     <= twelve;
        elsif (bup = '0' and bdn = '1') then
          next_state                <= flat;
        end if;
      when twelve            =>
        if (bup = '1' and bdn = '0') then
          next_state                <= twelve;
        elsif (bup = '0' and bdn = '1') then
          next_state           <= six;
        end if;
      when nsix         =>
        if (bup = '1' and bdn = '0') then
          next_state           <= flat;
        elsif (bup = '0' and bdn = '1') then
          next_state      <= ntwelve;
        end if;
      when ntwelve =>
        if (bup = '1' and bdn = '0') then
          next_state      <= nsix;
        elsif (bup = '0' and bdn = '1') then
          next_state <= ntwelve;
        end if;

    end case;
  end process process2;
  
  process3 : process (state)
  begin
    case state is
      when flat    => wp <= "011000100001";
      when six     => wp <= "011000100001";
      when twelve  => wp <= "011000100001";
      when nsix    => wp <= "011000011111";
      when ntwelve => wp <= "110000110111";
                      
    end case;
  end process process3;
end Behavioral;