Help me to draw a standard cell layout

hi all,
I am fresher and I have to draw layout for standard cells. Pls help me to resolve this issue.
1. What should be height and width of standard cell for .18µ and .25µ technology? Is any thumb rule?
2. What is DFM, ACLV, and ACMV issue in layout?
3. For different technology, what should be the value of input frequency and load capacitance?
Regards,
Raj

Re: Standard cell layout

DFM = Design For Manufacturability.

I think it's a set of rules given by the fab to guarantee a high yield from the layout ( such as for example placing two contacts instead of a single contact )

Not familiar with the other terms/questions, sorry[/u]

Re: Standard cell layout

There are no thumb rules specific to each process which could determine the height of a standard cell.The height basically depends upon the performance and power characteristics of the library which is going to be used.
If you need high speed layouts you need to used layouts with smaller heights with multiple fingering in the output stage.IF you need to increase the delay then vice versa!!!!

Re: Standard cell layout

hi actually there are some guide lines provided by mosis foundary for design of standard cells in sub micron technologies you can find the document in mosis.org->design flows
hope this helps

Re: Standard cell layout

their are some rules to be fllowed while drawing standard cells.

for TSMC 0.25um.

cell width -integer multiples of 9lamda.
cell height- 108 lamda= 12*routing grid.

metal pitch -metal1 to metal2 9lamda.
core cell orgin 0lamda.0lamdha.

via metal enclosure size- 5*5 lamda^2.

pereefered metal direction- m1 vertical ;m2 horizontal.m1 could be exempted from this rule

cell edge- nearest metal distance: 9lamda to center,7lamda to edge.

Re: Standard cell layout

1. What should be height and width of standard cell for .18µ and .25µ technology? Is any thumb rule?
A: There is no specific thumb rule for this. It all depends on the process that you are working on as well as the foundry. As already mentioned, a low power process will have smaller hieght when compared to a generic process.

2. What is DFM, ACLV, and ACMV issue in layout?
A: DFM is Design for Manufacturability
ACLV: Across Chip Line Variation (Fabrication issue like etching effects that comes up in 65 nm and advanced technologies)
ACMV: Across Chip Mobility Variation ( Hole and Mobility balancing technique )

3. For different technology, what should be the value of input frequency and load capacitance?
A: Again a foundry parameter with wich you have nothing to do.

--cmos_dude

Re: Standard cell layout

gharuda said:

their are some rules to be fllowed while drawing standard cells.

for TSMC 0.25um.

cell width -integer multiples of 9lamda.
cell height- 108 lamda= 12*routing grid.

metal pitch -metal1 to metal2 9lamda.
core cell orgin 0lamda.0lamdha.

via metal enclosure size- 5*5 lamda^2.

pereefered metal direction- m1 vertical ;m2 horizontal.m1 could be exempted from this rule

cell edge- nearest metal distance: 9lamda to center,7lamda to edge.

Click to expand...

Hi Gharud,

The above design rules which you are talking about is outdated. Now the new rules have come up which are called as Micron rules. I have never seen it , I have worked on Cadence tools, I don't know on which tool specifically you are talking about these Lambda Based rules.
Regards
vlsitechnology

---------- Post added at 11:20 ---------- Previous post was at 11:18 ----------

Hi Gharuda,

The above design rules which you are talking about is outdated. Now the new rules have come up which are called as Micron rules. I have never seen it , I have worked on Cadence tools, I don't know on which tool specifically you are talking about these Lambda Based rules.
Regards
vlsitechnology