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`define :
`define is a macro substitution like you #define in C language.
This defines a text macro that will be substituted wherever it occurs. Like
`define NPN npn_transistor will replace all `NPN with npn_transistor.
It is a text macro substitution.
parameter
parameter is used to define a constant whose value doesnot change during runtime.
So once you define a parameter it remains constant. The difference here is that this is a value substitution and it can be used for module instantiations as a changing value.
i.e. For each instantiation you can have a parameter value based on defparam definition.
parameter d = 5
# d;
a <= d;
this puts 5 in a after 5 simulation time.
Thats it. for further reference the LRM file for verilog. You can find the syntax and usage in it.
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