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Companies proprietry tools are available for timing analysis
but as they are proprietry they are not availabel to all and i don't think that any one have that information about that tools
but it's critical to analyse asynchrnous circuit
Latch based designs give better timing & performance because of its clocking nature ,but the area overhead will be more.
Latch based LSSD design concept is propreitry of IBM & they had their own tools to handle it.Recently few of its tools are taken over by Cadence .The one I know is encounter test architect .
Hi ,
When the dft implemented is latch based ,which I mean all the scan elements are Latch'es , then the design is also Latch based design .For implementing dft logic encounter test architect is used .
I'm not sure which tool is used for Timing analysis for a Latch based design .
If your design includes asynchronous logic, I suggest that you use latch to do some logic about interface, but I can not believe a full latched chip which does not use Dff triggers
Latch based designs give better timing & performance because of its clocking nature ,but the area overhead will be more.
Latch based LSSD design concept is propreitry of IBM & they had their own tools to handle it.Recently few of its tools are taken over by Cadence .The one I know is encounter test architect .
so it has problems in timing analysis and also area overhead...okays
but someone said that it needs multiplephase clock...i'm confused somehow...isn't this latch based design...so it's asynchronous...???
Hi ,
The latch based designs are not intended for specific type of logic or design , it can be used in any application .The clocking scheme will be pretty complicated because of multiphase clock input to the latches .
This latch has two latches inside , one acting as master & other one as slave .This latch is controlled by minimum of 3 clocks ( A,B,C ) .This is one of the many type of latches.There are some latches which acts like D-FF .
For simple understanding you can see the doc attached below .
CPU-designers (Intel, AMD, TI, etc.) have used asynchronous-design strategies to achieve very specific performnace goals, but that's in the territory of PhD and other advanced engineers...not for 'average' persons
For example, the Intel Pentium/4 contained a large portion of 'self-resetting domino' gate-layouts in the speed-critical ALU/datapath. Intel also had an army of engineers to conduct the design/layout/verification of that block of logic, and it's no easy job.
Do a google.com search for 'Pentium self-resetting domino' -- there are a few overviews on the web. To get more detailed papers, you'll need an IEEE or ISSCC subscription.
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